ld7578 Leadtrend Technology, ld7578 Datasheet - Page 11

• Manufacturer Part Number: ld7578
• Description: Green-mode Pwm Controller With Hv Start-up Circuit And Otp Protection
• Manufacturer: Leadtrend Technology

Oscillator and Switching Frequency
The switching frequency of the LD7578 is fixed as 65KHz
internally to provide the optimized operations by
considering the EMI performance, thermal treatment,
component sizes and transformer design.
Internal Slope Compensation
Stability is crucial for current mode control when it
operates at more than 50% of duty-cycle. To stabilize the
control loop, the slope compensation is required in the
traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In the
LD7578, the internal slope compensation circuit has been
implemented to simplify the external circuit design.
On/Off Control
Pulling COMP pin below 1.2V will turn off the LD7578 and
disable the gate output pin of the LD7578. The off-mode
Leadtrend Technology Corporation
LD7578-DS-00 October 2008
Fig. 16
www.leadtrend.com.tw
11
will be released when the pull-low signal at COMP pin is
removed.
Dual-Oscillator Green-Mode Operation
Lots of topologies have been implemented in different
chips for the green-mode or power saving requirements
such as “burst-mode control”, “skipping-cycle mode”,
“variable off-time control “…etc. The basic operation
theory of all these approaches intends to reduce the
switching cycles under light-load or no-load condition
either by skipping some switching pulses or by reducing
the switching frequency.
What the LD7578 uses to implement the power-saving
operation is Leadtrend Technology’s own IP. By using this
dual-oscillator control, the burst -mode frequency can be
well controlled and further to avoid the generation of
audible noise.
Over Load Protection (OLP)
To protect the circuit from being damaged under over load
condition or short condition, a smart OLP function is built
in with the LD7578, as shown in Figure 17 shows the
waveforms of the OLP operation. If output voltage drops,
the feedback system tends to force the voltage loop
toward the saturation (6V) and then pulls the voltage of
COMP pin to high. Whenever the V
threshold 5.0V and continues over 30mS, OLP is
activated and then turns off the gate output to stop the
switching of power circuit. The 30mS delay time is to
prevent the false trigger from the power-on and turn-off
transient.
A divide-2 counter is implemented to reduce the input
average power under OLP behavior. Whenever OLP is
activated, the output is latched off and the divide-2
counter starts to count the number of UVLO(off).
latch is released if the 2nd UVLO(off) point is counted
then the power circuit is recovered to switch again.
COMP
LD7578
trips to the OLP
The