az100lvel16vr Arizona Microtek, Inc., az100lvel16vr Datasheet

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az100lvel16vr

Manufacturer Part Number
az100lvel16vr
Description
Ecl/pecl Oscillator Gain Stage & Buffer With Selectable Enable
Manufacturer
Arizona Microtek, Inc.
Datasheet
FEATURES
DESCRIPTION
function. The Q
MLP 16, 3x3 mm Package (VRL) or DIE (VRX)
the Q/Q ¯ outputs. The enable truth table on the next page shows the operating modes. Leaving EN-SEL open (NC)
selects PECL/ECL operation for the EN pad/pin. In this mode the Q
open (NC) or set to a PECL/ECL low.
V
HG
connected to the opposite supply.
V
next page for the supported values. External resistors may also be used to increase pull-down current to a maximum
total of 25mA for the Q/Q ¯ outputs.
left open (NC), the output current sources are disabled and the Q
is connected to V
resistor between V
1
date codes.
This operational mode (EN-SEL to V
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
EE
BB
outputs are enabled when EN is left open.
, the Q
Green and RoHS Compliant /
Lead (Pb) Free Packages Available
Enhanced Enable Operation
High Bandwidth for ≥1GHz
Similar Operation as AZ100EL16VO
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a MLP 16 or MLP 8
Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable
The AZ100LVEL16VR provides a selectable Q
Connecting EN-SEL to V
The AZ100LVEL16VR also provides a V
Outputs Q/Q ¯ each have a selectable on-chip pull-down current source. See the current source truth table on the
Each of the Q
pin supports 1.5mA sink/source current. V
HG
/Q ¯
HG
HG
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
EE
/Q ¯
HG
outputs are disabled when EN is left open (NC). When EN-SEL is tied to V
EEP
, the current sources are activated. The Q
HG
/Q ¯
and V
HG
outputs have voltage gain several times greater than the Q/Q ¯ outputs.
outputs has an optional on-chip pull-down current source of 10 mA. When pad/pin V
EE
.
CC
CC
, V
or V
EE
BB
AZ100LVEL16VR
or V
) is not supported for date codes prior to 0428 (July 2004). EN-SEL to V
BB
selects CMOS operation for the EN pad/pin. When EN-SEL is tied to
1
MLP 16 (3x3)
MLP 16 (3x3) RoHS
Compliant / Lead
(Pb) Free
MLP 8 (2x2) Green /
RoHS Compliant /
Lead (Pb) Free
DIE
DIE
BB
BB
www.azmicrotek.com
This default logic condition can be overridden by a ≤20kΩ resistor
and 470Ω internal bias resistors from D to V
should be bypassed to ground or V
1
2
3
4
PACKAGE
HG
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack. Die thickness 14 mils.
Die on 7 inch Tape & Reel, 3k parts per reel. Die thickness 14 mils.
/Q ¯
HG
HG
enable that allows continuous oscillator operation via
/Q ¯
HG
PACKAGE AVAILABILITY
HG
/Q ¯
AZ100LVEL16VRL
AZ100LVEL16VRL+
AZ100LVEL16VRNEG
AZ100LVEL16VRXP
AZ100LVEL16VRXR
pull-down current can be decreased by using a
HG
HG
operate as standard PECL/ECL. When V
/Q ¯
PART NO.
HG
outputs are enabled when EN is left
ARIZONA MICROTEK, INC.
CC
with a 0.01 μF capacitor.
AZM
16R
<Date Code>
AZM+
16R
<Date Code>
R5G
<Date Code>
N/A
N/A
MARKING
BB
CC
and D ¯ to V
or V
EE
is supported for all
BB
, the Q
BB
1,2
1,2
1,2
3
4
NOTES
. The
EEP
HG
EEP
/Q ¯
is

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az100lvel16vr Summary of contents

Page 1

... S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website DESCRIPTION The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable function. The Q /Q ¯ outputs have voltage gain several times greater than the Q/Q ¯ outputs. HG ...

Page 2

... AZ100LVEL16VR 4mA EA 470 CMOS / TTL THRESHOLD AZ100LVEL16VRL, VRX EN-SEL 1 1 EN-SEL connections must be ≤1Ω. 2 Date codes prior to 0428 do not support this operating mode. CURRENT SOURCE TRUTH TABLE CS-SEL Q NC 4mA typ ...

Page 3

... AZ100LVEL16VR D EN (EN-SEL NC) EN (EN-SEL CONNECTED EL16VR DIE SIZE: 950u X 940u DIE THICKNESS: 14 mils C BOND PAD: 85u X 85u Notes: 1. Other die thicknesses available. Contact factory for further information. 2. The die backside may be left open or connected to V ...

Page 4

... Input Levels) www.azmicrotek.com 4 output is forced high and the Q ¯ HG PIN DESCRIPTION FUNCTION Data Input Data Output Data Outputs w/High Gain Reference Voltage Output Enable Input Negative Supply Positive Supply AZ100LVEL16VRNE MLP 8, 2x2 Leave Pad open or connect to ...

Page 5

... AZ100LVEL16VR Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol V PECL Power Supply CC V PECL D/D ¯ Input Voltage D/D ¯ V PECL EN Input Voltage EN V ECL Power Supply EE V ECL D/D ¯ Input Voltage D/D ¯ V ECL EN Input Voltage EN Output Current, Q/Q ¯ ...

Page 6

... AZ100LVEL16VR 100K PECL DC Characteristics (V Symbol Characteristic 1,2 V Output HIGH Voltage OH 1,2 V Output LOW Voltage OL 1 Input HIGH Voltage 3 V D/D ¯ (PECL (CMOS) 1 Input LOW Voltage 3 V D/D ¯ (PECL (CMOS Reference Voltage BB Input HIGH Current Input LOW Current (PECL) ...

Page 7

... AZ100LVEL16VR Typical Large Signal Outputs, Q 1000 900 800 700 600 500 400 300 200 100 0 0 500 Measured with 750mv differential input via 50 Ω resistors. May 2008 * REV - 17 1000 1500 2000 FREQUENCY (MHz) NC, Q EEP www.azmicrotek.com 7 /Q ¯ 2500 ...

Page 8

... AZ100LVEL16VR 0.95 0.9 0.85 0.8 0.75 0.7 50 150 250 350 (50 Ω external AC, 4 & 8mA internal DC Load on Q ¯ ) 0.025 0.02 0.015 0.01 0.005 0 50 150 250 350 (50 Ω external AC, 4 & 8mA internal DC Load on Q ¯ ) May 2008 * REV - 17 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) S11 ¯ ...

Page 9

... AZ100LVEL16VR 150 250 (50 Ω external AC, 4 & 8mA internal DC Load on Q ¯ ) 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 50 150 (50 Ω external AC, 4 & 8mA internal DC Load on Q ¯ ) May 2008 * REV - 17 350 450 550 650 750 850 950 1050 1150 Frequency (MHz) S21 ¯ ...

Page 10

... AZ100LVEL16VR 3 CMOS Application Circuit for CMOS Inputs 1 R1 should be chosen so that the input swing on the D input with respect to D ¯ the range of ±80 to ±1000 mV, per the AC Characteristics table and the D input is < ±750 mV with respect to V Recommended Component Values for CMOS Single Ended Inputs ...

Page 11

... AZ100LVEL16VR DIE ID Package Suffix Reel Diameter X (Die) R 7” May 2008 * REV - 17 DIE ON TAPE OREINTATION Direction of Feed Quantity Carrier Tape Width 3000 8mm www.azmicrotek.com 11 Carrier Tape Pitch 4mm ...

Page 12

... AZ100LVEL16VR Pin 1 Dot By Marking 0.250±0.050 0.500 bsc 0.750±0.050 0.000-0.050 Note: All dimensions are in mm May 2008 * REV - 17 PACKAGE DIAGRAM MLP 8 2x2mm 2.000±0.050 MLP 8 2.000±0.050 (2x2mm) TOP VIEW 0.350±0.050 1.200±0.050 ...

Page 13

... AZ100LVEL16VR D 2. INDEX AREA (D aaa C TOP VIEW 2 x aaa C 4. NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. 2. THE TERMINAL #1 AND PAD NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM PAD TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS ...

Page 14

... AZ100LVEL16VR Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages ...

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