glt625608 G-Link Technology Corporation, glt625608 Datasheet - Page 8

• Manufacturer Part Number: glt625608
• Description: 32k X 8 Slow Speed Cmos Static Ram
• Manufacturer: G-Link Technology Corporation

WRITE CYCLE 2
Note:
1.
2. The internal write time of the memory is defined by the overlap of
3. T
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
5. If the
6.
7. D
8. D
9. If
10. Transition is measured 200mV from steady state with C
11. t
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
the outputs must not be applied.
transition, outputs remain in a high impedance state.
signals of opposite phase to the outputs must not be applied to them.
WE
OE
CW
WR
OUT
OUT
CE
G -LINK
is measured from
is continuously low (
is measured from the earlier of
must be high during address transitions.
is the same phase of write data of this write cycle.
is the read data of next address.
CE
is low is high during this period, I/O pins are in the output state. Then the data input
low transition occurs simultaneously with the
(1,6)
CE
OE
Web : www.glink.com.tw
going low to the end of write.
G-Link Technology Corporation,Taiwan
=V
IL
).
TEL : [phone]
CE
or
WE
- 8 -
Email : [e-mail]
going high at the end of write cycle.
32K x 8 SLOW SPEED CMOS STATIC RAM
WE
L
=5pF.
low transitions or after the
CE
active and
GLT625608
WE
Feb, 2004(Rev. 1.2)
WE
low. All