ch7318c Chrontel, ch7318c Datasheet

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ch7318c

Manufacturer Part Number
ch7318c
Description
Ch7318c Ac Coupled Hdmi Level Shifter
Manufacturer
Chrontel
Datasheet

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1.0 F
Chrontel
201-1000-006
Converts low-swing AC coupled differential input to
HDMI 1.3 compliant open-drain current steering Rx
terminated differential output.
HDMI TMDS level shifting operation up to 1.65Gb/s
per lane (165MHz pixel clock).
Enable feature to turn off TMDS inputs and outputs and
to enter low-power state.
Transparent operation: no re-timing or configuration
required.
Inter-Pair added skew < 250ps
Intra-Pair added skew < 10ps
Switching power only from a single 3.3V supply.
Integrated 50-ohm termination resistors for AC coupled
differential Inputs.
Pass-gate voltage limiters allow 3.3V termination on
GMCH pins, 5V DDC termination on HDMI connector
pins.
Human Body Model ESD protection: 8kV for all output
pins and 2kV for all other pins.
Level shifter for HDMI 1.3 HPD.
Integrated pull-down resistor on HPD_SINK input
guarantees “input low” when no display is plugged in.
Driver’s current adjustment +10%.
Inverting buffer for HPD signal
Configurable pre-emphasis level (0dB, 2.0dB, 4.0 dB,
& 6.0dB)
Offered in a 48-Pin QFN Package.
EATURES
Rev. 2.1,
CH7318C AC Coupled HDMI Level Shifter
1/23/2009
2.0 G
CH7318C is a high speed HDMI level shifter that
converts low-swing AC coupled differential input to
HDMI 1.3 compliant open-drain current steering Rx
terminated differential output.
The CH7318C features integrated parallel termination
resistors (50-ohm), which eliminate the requirement for
external termination resistors on the TMDS differential
output pins.
protection for DDC channels as well as TMDS signal
lines. In addition, the DDC_EN pin controls bias
voltage to enable or disable the DDC passgate level
shifter gates. The OE* pin is a two- state output enable
control for the differential input and the TMDS signal
output. It can activate IN_Dx pins and OUT_Dx pins
or switch them into high impedance. A unique pre-
emphasis control is also implemented into CH7318C;
this feature has four- level adjustment to increase rise
and fall times which are degraded during the
transmission over a long trace on PCB.
The device operates from a single +3.3V supply, and is
characterized the operation temperature range from
-10 °C to 50 °C (ambient temperature). The CH7318C
is available in a 48-Pin QFN package.
ENERAL
This device has incorporated a ESD
D
ESCRIPTION
CH7318C
1

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ch7318c Summary of contents

Page 1

... PCB. The device operates from a single +3.3V supply, and is characterized the operation temperature range from -10 ° °C (ambient temperature). The CH7318C is available in a 48-Pin QFN package. 1 ...

Page 2

... SCL_SOURCE SDA_SOURCE 2 3.3V 50 ohm x 2 Pre-emphasis 3.3V 50 ohm x 2 Pre-emphasis 3.3V 50 ohm x 2 Pre-emphasis 3.3V 50 ohm x 2 Pre-emphasis HPD Buffer 100k ohms DDC Level Shifter Figure 1: CH7318C Block Diagram 201-1000-006 CH7318C * OE OUT_D1- OUT_D1+ OUT_D2- OUT_D2+ OUT_D3- OUT_D3+ OUT_D4- OUT_D4+ HPD_SINK SCL_SINK SDA_SINK DDC_EN Rev. 2.1, ...

Page 3

... CHRONTEL 3 3.1 Package Diagram 1 GND 2 VCC3V 3 TRIM 4 HPDEN 5 GND 6 Analog1(REXT) 7 HPD_SOURCE 8 SDA_SOURCE 9 SCL_SOURCE VCC3V GND 12 201-1000-006 Rev. 2.1, 1/23/2009 Chrontel CH7318C Figure 2: 48-Pin QFN Pin Out CH7318C 36 GND 35 CCT2 34 CCT1 33 VCC3V 32 DDC_EN 31 GND 30 HPD_SINK 29 SDA_SINK 28 SCL_SINK 27 GND 26 VDD3V OE ...

Page 4

... DDC Clock I/O. Pulled up by external termination to 5V. Connected to SCL_SOURCE through voltage-limiting by integrated NMOS passgate. 5V DDC Data I/O. Pulled up by external termination to 5V. Connected to SDA_SOURCE through voltage-limiting by integrated NMOS passgate. 201-1000-006 CH7318C Output current Default +10% HPD_SOURCE Non-inverting output (in terms of HPD_Sink) Inverting output (in terms of ...

Page 5

... Low-swing diff input from GMCH PCIe outputs. IN_D2+ makes a differential pair with IN_D2-. Low-swing diff input from GMCH PCIe outputs. IN_D3+ makes a differential pair with IN_D3-. Low-swing diff input from GMCH PCIe outputs. IN_D4+ makes a differential pair with IN_D4-. CH7318C Passgate Disabled Enabled Pre-emphasis level 0dB(default) ...

Page 6

... HPD_SINK input and HPD_SOURCE output are not affected by OE*. SCL_SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE*. TMDS_OUTx Notes High-Z Device disabled. Low power state. Internal bias currents are disabled. Enabled Level shifting mode enabled. 201-1000-006 CH7318C Rev. 2.1, 1/23/2009 ...

Page 7

... CHRONTEL 4.5 Pre-emphasis Function The CH7318C has an advanced pre-emphasis control mechanism for reducing jitter and increasing rise/fall times from long or lossy transmission high speed signal. Two pins are used to configure the pre-emphasis level for OUT_Dx outputs: Table 4: Pre-emphasis Selection Table CCT1 CCT2 ‘ ...

Page 8

... Tbit is determined by the display mode. Nominal bit rate ranges from 250Mb/s to 1.65Gb/s per lane. (1.65Gb/s supported on both TMS and muxed outputs). Nominal Tbit at 1.65Gb/s=606ps. 540ps =606ps-10%. 0.175 1.2 V VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|. Applies to IN_D signals. 201-1000-006 CH7318C Typ Max Units 5.0 V Indefinite Sec 85 °C 150 ° ...

Page 9

... AVcc-400mV 450 500 600 10 206 0.4Tbit 206 0.4Tbit 10 250 10.8 CH7318C Comments The level shifter may add a maximum of 0.02UI jitter VCM-AC-pp = |VRX-D+ + VRX-D – VRX-CM-DC. VRX-CM-DC = DC(avg) of |VRX-D++ VRX-D VCM-AC-pp includes all frequencies above 30kHz. Required IN_D+ as well as IN_D- DC impedance (50 +/- 20% tolerance). ...

Page 10

... Comments 0 µA Measured with OE Min Typ Max Units Comments 80k 100k 120k Guarantees HPD_SINK is LOW when no display is plugged in. 201-1000-006 CH7318C V max and min IH-HPD IL-HPD from OH-HPDB OL-HPDB to V OL-HPDB OH-HPDB V max and min IH-EN IL-EN Rev. 2.1, 1/23/2009 ...

Page 11

... MAX 5.25 Notes: 1. Conforms to JEDEC standard JESD-30 MO-220. 201-1000-006 Rev. 2.1, 1/23/2009 BOTTOM VIEW BOTTOM VIEW BOTTOM VIEW BOTTOM VIEW C Figure 3: 48 Pin QFN Package SYMBOL 2.25 0.18 0.5 0.2 5.25 0.30 CH7318C B B 0.30 0.7 0 0.203 0.50 0.8 0.05 11 ...

Page 12

... CHRONTEL 7 EVISION ISTORY Table 12: Revisions Rev. # Date Section 1.0 1/23/2008 All 2.0 4/25/2008 All 3.0 3.2 2.1 1/23/2009 5.1, 5.1. 12 Description Initial release. Change to CH7318C. Add Pin 35 CCT2, Pin34 CCT1 and move TRIM to Pin3. Update Table 1. Pin3, Pin34 and Pin35. Update temperature range. 201-1000-006 CH7318C Rev. 2.1, 1/23/2009 ...

Page 13

... Chrontel International Limited ©2009 Chrontel - All Rights Reserved. 201-1000-006 Rev. 2.1, 1/23/2009 Disclaimer ORDERING INFORMATION Number of Package Type Pins Lead-free QFN 48 Lead-free QFN 48 in Tape & Reel Chrontel 129 Front Street, 5th floor, Hamilton, Bermuda HM12 www.chrontel.com E-mail: sales@chrontel.com CH7318C Voltage Supply 3.3V 3.3V 13 ...

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