DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 26

• Manufacturer Part Number: DS26303G-120
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 5-2. Secondary Register Set
Single Rail-Mode Select
Line Code Selection
Not Used
Receive Power-Down Enable
Transmit Power-Down Enable
Excessive Zero Detect Enable
Code Violation Detect Enable Bar
Not Used
Address Pointer for Secondary Register Set
Table 5-3. Individual LIU Register Set
Individual JA Enable
Individual JA Position Select
Individual JA FIFO Depth Select
Individual JA FIFO Limit Trip
Individual Short Circuit Protection Disable
Individual AIS Select
Master Clock Select
Global Management Register
Reserved
Reserved
Bit Error Rate Tester Control Register
Line Violation Detect Status
Receive Clock Invert
Transmit Clock Invert
Clock Control Register
RCLK Disable Upon LOS Register
Global Interrupt Status Control
Address Pointer for Secondary Register Set
NAME
NAME
SYMBOL
SYMBOL
Reserved
Reserved
CVDEB
IJAFDS
RDULR
IJAFLT
ISCPD
IAISEL
SRMS
RCLKI
RPDE
ADDP
TCLKI
TPDE
EZDE
IJAPS
BTCR
ADDP
LVDS
GMR
GISC
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
IJAE
CCR
LCS
MC
—
—
26 of 97
07–1E
HEX
08–0B
0C–0F
01
02
03
06
1F
00
04
05
HEX
00
01
02
04
05
06
07
10
12
13
14
15
16
1E
1F
03
A7–A0 (HEX)
INTERFACE
PARALLEL
xxx00111–
A7–A0 (HEX)
INTERFACE
xxx00000
xxx00001
xxx00010
xxx00011
xxx00100
xxx00101
xxx00110
xxx11110
xxx11111
PARALLEL
xxx01000–
xxx01100–
xxx00000
xxx00001
xxx00010
xxx00100
xxx00101
xxx00110
xxx00111
xxx01011
xxx01111
xxx10000
xxx10010
xxx10011
xxx10100
xxx10101
xxx10110
xxx11110
xxx11111
xxx00011
ADDRESS
ADDRESS
A7–A1 (HEX)
A7–A1 (HEX)
INTERFACE
INTERFACE
xx00111–
xx01000–
xx01100–
xx10110
SERIAL
xx00000
xx00001
xx00010
xx00011
xx00100
xx00101
xx00110
xx11110
xx11111
SERIAL
xx00000
xx00001
xx00010
xx00011
xx00100
xx00101
xx00110
xx00111
xx01011
xx01111
xx10000
xx10010
xx10011
xx10100
xx10101
xx11110
xx11111
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
R
R
R