DS90UR124IVS NSC [National Semiconductor], DS90UR124IVS Datasheet
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DS90UR124IVS
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DS90UR124IVS Summary of contents
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DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream sim- plifies transferring a 24-bit ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVDS DC SPECIFICATIONS V Differential Threshold High TH Voltage V Differential Threshold Low TL Voltage I Input Current IN V Output Differential Voltage OD (D )–(D ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t LVDS Low-to-High Transition Time LLHT t LVDS High-to-Low Transition Time LHLT t D (0:23) Setup to TCLK DIS (0:23) Hold from ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t R (0:7) Setup Data to ROS OUT RCLK (Group (0:7) Hold Data to ROH OUT RCLK (Group (8:15) ...
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AC Timing Diagrams and Test Circuits FIGURE 2. Deserializer Output Checkerboard Pattern FIGURE 3. Serializer LVDS Output Load and Transition Times FIGURE 4. Deserializer LVCMOS/LVTTL Output Load and Transition Times www.national.com FIGURE 1. Serializer Input Checkerboard Pattern 6 20194502 20194503 ...
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AC Timing Diagrams and Test Circuits FIGURE 5. Serializer Input Clock Transition Times (Continued) FIGURE 6. Serializer Setup/Hold Times 7 20194506 20194507 www.national.com ...
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AC Timing Diagrams and Test Circuits FIGURE 7. Serializer TRI-STATE Test Circuit and Delay FIGURE 8. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays www.national.com (Continued) 8 20194508 20194509 ...
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AC Timing Diagrams and Test Circuits (Continued) FIGURE 9. Serializer Delay FIGURE 10. Deserializer Delay 9 20194510 20194511 www.national.com ...
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AC Timing Diagrams and Test Circuits FIGURE 11. Deserializer Setup and Hold Times and PTO, PTOSEL = H Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI) Group 2 will be latched ...
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AC Timing Diagrams and Test Circuits FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay (Continued) 20194513 11 20194514 www.national.com ...
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AC Timing Diagrams and Test Circuits FIGURE 15. Transmitter Output Eye Opening (TxOUT_E_O) FIGURE 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window VOD = (D ) – OUT+ OUT− Differential output signal is shown – ...
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Pin Descriptions Pin # Pin Name I/O/PWR DS90UR241 SERIALIZER PIN DESCRIPTIONS 22 VDDDR VDD 21 VSSDR GND 16 VDDPT0 VDD 17 VSSPT0 GND 14 VDDPT1 VDD 15 VSSPT1 GND 30 VDDT VDD 31 VSST GND 7 VDDL VDD 6 VSSL ...
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Pin Descriptions (Continued) Pin # Pin Name I/O/PWR DS90UR124 DESERIALIZER PIN DESCRIPTIONS 46 VDDR0 VDD 47 VSSR0 GND 40 VDDOR1 VDD 39 VSSOR1 GND 26 VDDOR2 VDD 25 VSSOR2 GND 11 VDDOR3 VDD 12 VSSOR3 GND 53 R LVDS_I IN+ ...
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Pin Descriptions (Continued) Pin # Pin Name I/O/PWR DS90UR124 DESERIALIZER PIN DESCRIPTIONS 1-6, RESRVD NC 17, 18, 33, 34 Description RESeRVeD - no connect (n/c) 15 www.national.com ...
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Pin Diagram www.national.com Serializer - DS90UR241 16 20194519 ...
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Pin Diagram (Continued) Deserializer - DS90UR124 17 20194520 www.national.com ...
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Functional Description The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.032 Gbps throughput. The DS90UR241 transforms a ...
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Functional Description reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is driven low. In power- down, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing supply. To exit ...
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Functional Description 8-bit counter on ROUT[7:0] is used to represent the number of errors detected (0 to 255 max). The successful completion of the BIST test is reported on the PASS pin on the Deseri- alizer. The Deserializer’s PLL must ...
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Applications Information LVDS INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings — space between the pair — space between pairs — 3S ...
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Truth Tables Pin 9 Pin 18 TPWDNB DEN Pin 48 Pin 60 RPWDNB REN www.national.com TABLE 1. DS90UR241 Serializer Truth ...
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Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters only Order Number DS90UR241IVS NS Package Number VBC48A 23 www.national.com ...
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... DS90UR241 48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel, DS90UR241IVSX DS90UR124 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch, DS90UR124IVS DS90UR124 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel, DS90UR124IVSX National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications ...