DS99R124QSQ NSC [National Semiconductor], DS99R124QSQ Datasheet - Page 9

• Manufacturer Part Number: DS99R124QSQ
• Description: 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
• Manufacturer: NSC [National Semiconductor]

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at V
Operation Conditions at the time of product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: t
Note 6: t
Note 7: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V
mVp-p measured at the device V
frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz.
Note 8: Specification is guaranteed by characterization and is not tested in production.
Note 9: Specification is guaranteed by design and is not tested in production.
AC Timing Diagrams and Test Circuits
DDLT
DCCJ
is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
is the maximum amount of jitter between adjacent clock cycles.
DDn
pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise
FIGURE 1. Checkerboard Data Pattern
FIGURE 2. LVCMOS Transition Times
DDn
= 1.8V, V
9
DDTX
= 3.3V, V
DDIO
= 1.8V or 3.3V, Ta = +25 °C, and at the Recommended
DDn
30105205
(1.8V) supply with amplitude = 100
30105232
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