ip1718lf ETC-unknow, ip1718lf Datasheet
ip1718lf
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ip1718lf Summary of contents
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Smart Switch Controller Features Embeds 1.5 Mb packet buffer Handles MAC address entries Supports non-blocking wire speed operation Provides 16-port SS-SMII and 2-port MII Supports 2 ports selectable normal MII, reverse MII All I/O signals ...
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Table Of Contents Features .................................................................................................................................................................. 1 General Description................................................................................................................................................. 1 Table Of Contents.................................................................................................................................................... 2 Revision History....................................................................................................................................................... 3 1 Pin Diagram...................................................................................................................................................... 4 2 Block Diagram .................................................................................................................................................. 5 3 Pin description.................................................................................................................................................. 6 Pin description (continued)...................................................................................................................................... 7 Pin description (continued)...................................................................................................................................... 9 Pin description (continued).................................................................................................................................... ...
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Revision History Revision # IP1718 LF-DS-R01 Initial release. IP1718 LF-DS-R02 Functions for pin 117 & pin 119 are re-defined. The register 2 description is revised. Revise the timing chart of SCPUIO and the SCPUC. IP1718 LF-DS-R03 Revised the pin diagram. ...
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Pin Diagram M2RXD2 103 M2RXD3 104 M3RXC 105 M2TXC 106 M2TXD0/Port5_Pri_ON 107 M2TXD1/Port6_Pri_ON 108 M2TXD2/WRR_Ration_Set0 109 M2TXD3/WRR_Ration_Set1 110 M2TXEN 111 M2COL 112 GND 113 114 VDD18 115 VDD33 GND 116 P1TXD/1st MII_Force_Link 117 P1RXD 118 P2TXD/2nd MII_Force_Link 119 P2RXD ...
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Block Diagram PLL/ Clock generator Regulator EEPROM CPU Interface MAC Address Table Copyright © 2003, IC Plus Corp. PHY Control I/F Memory controller/ BIST Register Tx/Rx FIFO/DMA Address 10/100M Resolution MAC Engine 5/33 IP1718 LF Preliminary Data Sheet Frame ...
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Pin description Type Description P Positive power or ground Input pin; O:Output pin IL Input latched upon reset Pin No. Label SS-SMII 117, 119 P1TXD, P2TXD, 121, 123, P3TXD, P4TXD, 128, 7, P5TXD, P6TXD, 9, 11, ...
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Pin description (continued) Pin No. Label MII/Reverse MII 95 M1TXEN 94, 93, 92, 91 M1TXD[3:0] 84 M1RXDV 88, 87, 86, 85 M1RXD[3:0] 90 M1TXC 89 M1RXC 111 M2TXEN 110,109,108,1 M2TXD[3: M2RXDV 104,103,100,9 M2RXD[3:0] 9 106 M2TXC 105 M2RXC ...
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IO_PWR 67 REG18 50, 53 N.C Copyright © 2003, IC Plus Corp. I Power selection for I/O pad. 0:1.8V; 1:3.3V. O 1.8V regulator control. This pin can be connected to the base of the PNP transistor to generate the ...
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Pin description (continued) Pin No. Label Power & Ground 68 VDDPLL 69 GNDPLL 4,37,57,80,114 VDD18 3,38,58,81,113 GND18 2,23,39,52,66,8 VDD33 3,101,115 1,24,40,51,65,8 GND33 2,102,116 Power On setting. These pins’ state will be latched upon reset 117 1st MII_Force_Link 119 2nd MII_Force_Link ...
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Pin description (continued) Pin No. Label Power On setting. These pins will be latched upon reset (continued) 41 AGING_OFF 43 HOME_VLAN_EN 47, 45 TRUNK_0_ON[1:0] 54 BPDU_BCST_OFF 59 TAG_PRI_ON 61 IP_PRI_ON 63 FAST_TEST_MODE IL, PD Reserved for IC test. 108,107,94,93, PORT_PRI_ON[5:0] ...
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Functional Description 4.1 Medium Access Control(MAC) 4.1.1 Data Rate Control The IP1718 LF implements a sophisticated data rate control mechanism, which is very useful for the bandwidth-limited network. By controlling both the ingress data rate and the egress data ...
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Switch Engine and Queue Management 4.2.1 Store & Forward Mechanism The IP1718 LF utilizes the “store & forward” method to handle the switch engine. Each data packet will not be forwarded to the destination port until the entire packet ...
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Destination MAC Source MAC Address(6 bytes) Address(6 bytes) 802.1Q VLAN tag 3’b100 ~ 3’b111 Precedence IPv6 Traffic Class 6’b101110; 6’b001010; 6’b010010; Field & IPv4 TOS 6’b011010; 6’b100010; 6’b11x000 Table 4.3 Forwarding Priority for IP DS and 802.1Q VLAN tag The ...
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Trunk Channel Supporting trunk channels, the IP1718 LF provides a versatile configurations that fit many applications. Each trunk channel may comprise ports. The traffic of the destination port passing through the trunk channel ...
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The first in first out method will override the CoS setting and is not recommended when the CoS function is enabled. When the strict priority is enabled, the data packets stored in low priority queue will not be sent out ...
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System Operation 5.1 Reset and EEPROM Download Procedure The reset input should be kept at “0” for more than 1.6 microsecond after power up. After detecting the rising edge of reset input, the IP1718 LF will start downloading the ...
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The IP1718 LF can be enforced to run at a specified mode without referring to the PHY status. When enforced, the IP1718 LF will write the forced mode to the corresponding PHY through MDC/MDIO and poll the link status of ...
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RXDATA during the high pulse of RXSYNC. The RX_DV(receive data valid) status follows CRS and finally the 8-bit data. For a given PHY port, the SS-SMII consists of six signals. RXDATA-one bit data for receiver TXDATA- one bit ...
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Register Map R = Read ; W = Write ; R/W = Read/Write Register Address 01H Half duplex control Bit [0]: Drops the packet that encounters 16 successive collisions. 1: Drop; 0: Forward Bit [1]: Collision back off. 1: ...
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Register Address 03H Egress/Ingress data rate control. Bit[7:0]: Egress data rate control. Bit[15:8]: Ingress data rate control. The maximum ingress/egress byte number in one time unit is. Bit[15:8] * 512 for Ingress Bit[7:0] * 512 for Egress. The one time ...
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Register Address 26H VLAN Tag based priority enable for pot17 and port 18, 1 bit per port bit[9: disable 1: enable Other bits are reserved. 27H IP DS based priority enable for port16~pot1, 1 bit per port bit[15:0] ...
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Register Address 2FH bit[0] : Hash algorithm selection 0 : CRC mapping 1 : Direct mapping bit[1] : Address table aging function disable 0 : aging function enabled 1 : aging function disabled bit[3:2] : Trunk ID hash algorithm selection ...
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Register Address 34H VLAN group setting for port 1 (p16~p01) The bit 15 corresponds to port 16 and the LSB corresponds to port 1. 0: The data incoming from port 1 is NOT allowed to be forwarded to the corresponding ...
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Register Address 68H Trunk group 0 (p4, p3, p2, p1) setting port 1 ~ port 4 are the same trunk group and can be any combination to form a trunk. The trunk ID described below is derived by the algorithm ...
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Register Address 6BH Port Mirroring Configuration 0 bit[15:0] : p16~p01 monitored port (source port this port is not monitored 1 : this port is monitored The LSB corresponds to port 1. 6CH Port Mirroring Configuration 1 bit[9:8] : ...
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Register Address 74H Auto negotiation for port18~pot17, 1 bit per port bit[9: auto negotiation disable; Other bits are reserved. 75H Speed setting for port16~pot1, 1 bit per port bit[15: 10Mb 1: 100Mb The LSB corresponds to ...
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Register Address 80H CPU read/write PHY register command bit[4:0] : the PHY address bit[9:5] : the MII register address bit[12:10] : (Reserved) bit[13 the read/write command has been completed 0: not yet bit[14 read operation, 1: ...
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Electrical Characteristics 7.1 Absolute Maximum Rating Permanent device damage may occur if Absolute Maximum Ratings are applied. Functional operation should be restricted to the conditions as specified in the following section. Exposure to the Absolute Maximum Conditions for extended ...
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Rx_Clk RxSync RxData xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx PHY Management (MDIO) Timing Symbol T MDCK High Time ch T MDCK Low Time cl T MDCK cycle time cm T MDIO set up time MD_SU T MDIO ...
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CPU Serial Bus Timing Symbol T SCPUC cycle time S_C T Serial I/O set up time SIO_SU T Serial I/O hold time SIO_H T Serial I/O output delay time SIO_D SCPUC SCPUIO xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx (Input) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ...
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MII Receive Timing Symbol T Receive clock period 100Mbps MII RxClk T Receive clock period 10Mbps MII RxClk T MII_RXCLK falling edge to RXDV, RXD RxClk_D MII_RXCLK ...
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Order Information Part No. IP1718 128-PIN PQFP IP1718 LF 128-PIN PQFP Copyright © 2003, IC Plus Corp. Package Notice - Lead free 32/33 IP1718 LF Preliminary Data Sheet January 27, 2005 IP1718 LF-DS-R05 ...
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Package Detail 128 PQFP Outline Dimensions 128 Dimensions In Inches Symbol Min. Nom. Max. A1 0.010 0.014 0.018 A2 0.107 0.112 0.117 b 0.007 0.009 0.011 c 0.004 0.006 ...