A1240A-1CQ256B ACTEL [Actel Corporation], A1240A-1CQ256B Datasheet - Page 28
A1240A-1CQ256B
Manufacturer Part Number
A1240A-1CQ256B
Description
HiRel FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A1240A-1CQ256B.pdf
(98 pages)
- Current page: 28 of 98
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A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V
28
Parameter
Input Module Propagation Delays
t
t
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
t
t
f
Note:
1.
INYH
INYL
INGH
INGL
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
HEXT
P
MAX
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
Description
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input Low to High
Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
1
C C
(continued)
= 4.5 V, T
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
FO = 256
FO = 32
J
= 1 25° C)
Min.
13.8
11.5
12.2
5.7
6.0
5.7
6.0
0.0
0.0
8.6
‘–1’ Speed
Max.
10.9
13.3
16.3
13.3
16.5
4.0
3.6
6.9
6.6
5.8
6.7
7.5
8.2
0.6
3.1
87
82
Min.
13.8
13.5
14.3
6.7
7.1
6.7
7.1
0.0
0.0
8.6
‘Std’ Speed
Max.
12.9
15.7
19.2
15.7
19.5
4.7
4.3
8.1
7.7
6.9
7.8
8.8
9.7
0.6
3.1
74
70
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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