A25L40PT-F AMICC [AMIC Technology], A25L40PT-F Datasheet - Page 18

• Manufacturer Part Number: A25L40PT-F
• Description: 4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Sector Erase (SE)
The Sector Erase (SE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
Select (
Data Input (D). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
(
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
PRELIMINARY
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
(May, 2007, Version 0.4)
S
C
D
Notes: Address bits A23 to A19 are Don’t Care.
S
) must be driven Low for the
0 1
2 3 4
Instruction
5 6
7
17
MSB
23
23
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Sector Erase cycle (whose
duration is t
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Sector Erase (SE) instruction is executed only if all Block
Protect (BP2, BP1, BP0) bits are 0. The Sector Erase (SE)
instruction is ignored if one, or more, sectors are protected.
8
22 21
9
24-Bit Address
10
BE
) is initiated. While the Sector Erase cycle is in
3 2 1
28 29 30 31
0 0
AMIC Technology Corp.
A25L40P Series
S
) is