VN16118L1 VAISH [Vaishali Semiconductor], VN16118L1 Datasheet

VN16118L1

Manufacturer Part Number

VN16118L1

Description

Gigabit Ethernet Transceiver

Manufacturer

VAISH [Vaishali Semiconductor]

Datasheet

1.VN16118L1.pdf (10 pages)

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Applications

General Description

The VN16118 is a single chip,1.25 Gigabits per second Ethernet transceiver. It performs all the

functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified

by the IEEE 802.3z Gigabit Ethernet standard. These functions include parallel-to-serial and

serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization.

In addition, an internal loopback function is provided for system debugging.

The VN16118 is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point

applications. The device supports both 1000BASE-LX and 1000BASE-SX fiber-optic media,

and 1000BASE-CX copper media.

The transmitter section of the VN16118 accepts 10-bit wide parallel TTL data and converts it to

a high speed serial data stream.

incoming parallel data is latched into an input register, and synchronized on the rising edge of

the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125

MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used

to provide the high speed serial data output. The output is sent through a Pseudo Emitter

Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of

1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE

SX fiber optic medium.

The receiver section of the VN16118 accepts a serial PECL-compatible data stream at a 1.25

Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A Phase

Lock Loop (PLL) locks on to the incoming serial data stream, and recovers the 1.25 GHz high

speed serial clock and data. This is accomplished by continually frequency locking on to the

125 MHz reference clock, and by phase locking on to the incoming data stream. The serial

data is converted back to parallel data format. The ‘comma’ character is used to establish byte

alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are

alternately used to clock out the parallel data on the rising edge. This parallel data is sent to

the user in TTL-compatible form.

1999-12-15

Features

Gigabit Ethernet Up-links

High Speed Proprietary

interface

IEEE 802.3z Gigabit Ethernet

Compliant

Supports 1.25 Gbps Using NRZ Coding

over uncompensated twin-coax cable

Fully integrated CMOS IC

Low Power Consumption

ESD rating >2000V (Human Body

Model) or >200V (Machine Model)

Vaishali Semiconductor

747 Camden Avenue

The parallel data is encoded in 8b/10b format.

SERDES

Campbell

Page 1

Gigabit Ethernet Transceiver

CA 95008

Backplane Serialization

Bus Extender

5-Volt Input Tolerance

Fully Compatible with HP HDMP-

1636/HDMP-1646 and Vitesse

VCS7135 transceivers

Available in both 10 mm x 10 mm

and 14 mm x 14 mm LQFP

Packages

Ph. 408.379.2900

Fax 408.379.2937

VN16118

MDSN-0001-00

Preliminary

This

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VN16118L1 Summary of contents

Page 1

Applications Gigabit Ethernet Up-links High Speed Proprietary interface General Description The VN16118 is a single chip,1.25 Gigabits per second Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified by ...

Page 2

VN16118 Figure 1. Functional Block Diagram EWRAP 10 Input Data Latch TX<9:0> TX_CLK 62.5 MHz RX_CLK<1> RX_CLK<0> 62.5 MHz 10 RX<9:0> Output Latch 10 EN_CDET FRAME ENABLE COM_DET 1999-12-15 Vaishali Semiconductor l 747 Camden Avenue 10 Shift Registers TX PLL ...

Page 3

VN16118 Figure 2. Pin Configuration (Top View GND_ESD 1 TX<0> 2 TX<1> 3 TX<2> 4 VCC_ESD 5 TX<3> 6 TX<4> 7 TX<5> 8 TX<6> ...

Page 4

VN16118 Table 1. Pin Description Name Pin # Type GND_ESD 1, 14 Power VCC_ESD 5, 10 TX<0> 2 TTL Input TX<1> 3 TX<2> 4 TX<3> 6 TX<4> 7 TX<5> 8 TX<6> 9 TX<7> 11 TX<8> 12 TX<9> 13 GND_TXA 15 ...

Page 5

VN16118 Table1. (Continued) Name Pin# Type GND_RXT 33 Power 46, VCC_RXT 37, 42 RX<9> 34 TTL Output RX<8> 35 RX<7> 36 RX<6> 38 RX<5> 39 RX<4> 40 RX<3> 41 RX<2> 43 RX<1> 44 RX<0> 45 COM_DET 47 TTL Output VCC_RXF ...

Page 6

VN16118 Functional Block Description Input Data Latch The input data latch block latches the 10-bit TTL input parallel byte, TX<9:0>, on the rising edge of the 125 MHz user-provided TX_CLK into the holding registers. Parallel-to-Serial Converter The received 10-bit TTL ...

Page 7

VN16118 Table 3. Guaranteed Operating Rates + 3. 3. Parallel Clock Rate (MHz) Min. Max. 124.0 126.0 Table 4. AC Electrical Characteristics ...

Page 8

VN16118 Table 6. Transceiver Reference Clock Requirements + 3. 3. Symbol Parameter f Nominal Frequency (for gigabit Ethernet Compliance) F Frequency Tolerance tol Symm Symmetry (Duty Cycle) ...

Page 9

VN16118 Table 8. Receiver Timing Characteristics +70 C, Vcc = 3. 3.45 V Symbol Parameter [1] b_sync Bit Sync Time f_lock Frequency Lock at Powerup t Data Setup Before Rising Edge of RX_CLK ...

Page 10

... VN16118 TOP VIEW D D Figure 7. Mechanical Dimensions All dimensions are in millimeters PART D1/E1 D/E NUMBER VN16118L1 10 12 VN16118L2 14 16 Package follows JEDEC Standards Ordering Information Part Number No. of Pins VN16118L1 64 VN16118L2 64 1999-12-15 Vaishali Semiconductor l 747 Camden Avenue 0.2 0.5 1.0 0.127 0.35 0.8 1.0 0.127 ...

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