cx74063-26 Skyworks Solutions, Inc., cx74063-26 Datasheet - Page 12

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cx74063-26

Manufacturer Part Number
cx74063-26
Description
Transceiver Multi-band Gprs, Edge Applications With Power Ramping Controller Integrated Crystal Oscillator With Output
Manufacturer
Skyworks Solutions, Inc.
Datasheet

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Data Sheet I CX74063-26
The user must provide the following three parameters:
• The reference divider value, from 1 to 15
• The N-divider value, in a manner similar to an integer-N
• A fractional ratio
The generated frequency is given by the following equation:
where: f
UHF VCO Frequency Setting
For the receiver, to tune the receive frequency, f
frequency, f
12
MAY 16, 2003
synthesizer
f
f
VCO
VCO
N
FN = Fractional setting
R
f
=
=
VCO
REF
3
2
3
4
VCO
= Generated VCO frequency
= N-divider ratio integer part
= R-divider ratio
= Reference frequency
f
f
, as follows:
RX
RX
f
VCO
for GSM850/900
for DCS1800 and PCS1900
=
D1
Fractional-N
N
+
PLL
3
D2
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
5 .
+
R
FN
2
L/C Filter
22
Skyworks Solutions, Inc., Proprietary and Confidential
Ext
f
ref
UHF VCO
Phase
Detect
Figure 6. Transmitter Frequency Generation
RX
, set the VCO
+
f
VCO
Ext Loop
Filter
90
÷3
0
For the transmitter VCO frequency, refer to the equations
shown in Figure 6.
Digital Frequency Centering
The CX74063-26 uses a novel technique whereby the UHF VCO
frequency range is re-centered each time the synthesizer is
programmed. This technique is called Digital Frequency
Centering (DFC). The DFC technique:
• Extends the VCO frequency coverage
• Speeds up settling time
• Ensures robust performance since the VCO is always
Each time the synthesizer is programmed, the DFC circuit is
activated, and the VCO is centered to the programmed
frequency in less than 20 µs. After this, normal Phase Locked
Loop (PLL) operation is resumed and the fine settling of the
frequency is finalized. The DFC typically adjusts the VCO center
frequency to within a few MHz and no more than 5 MHz offset,
and presets the tuning voltage to the center of the range before
the PLL takes over. This speeds up frequency settling and
ensures that the PLL control voltage never operates close to
the rails.
Tx I
Tx Q
Tx VCO
X2
operated at the center of its tuning range.
X2
where:
f
GSM:f
DCS/PCS: f
f
Tx
Tx
= f
LO
LO
(2 D1 - D2)/D1
101514D 6_071101
= (f
VCO
LO
= (2f
)/3
VCO
)/3
103052A

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