mx98745 Macronix International Co., mx98745 Datasheet
mx98745
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mx98745 Summary of contents
Page 1
... EEPROM, EEPROM operation can be disabled by setting EECONF to low. This feature faciliates system modulization appli- cation. 8 scale of utilization LED is also provided by MX98745. They are 1%, 3%, 5%, 10%, 20%, 40%, 60% and 80+%. The defination for utiliztion is Mbs Received/100 Mb within one second sampling period. Meanwhile, RX/LINK, Par- tition, Isolation and Collision status are also provided through LED display ...
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... Port & Port 7 RX Relative FUN Port 7 Relative FUN Expansion Port Function ANYACT LED[8:0] LDSEL[2:0] EDAT[4:0] JAMO EDENL EDCRS EPCLK Figure 3-1 Block Diagram forMX98745 2 MX98745 RDAT0[4:0] RSCLK0 TDAT0[4:0] TXCLK (MII Only) RDAT7[4:0] RSCLK7 TDAT7[4:0] Utilization/ Status LED Display FUN REV. 1.4, JUL. 8, 1998 ...
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... IBMON 31 TSEL 32 TEST 33 XCOLED 34 SCRCTRL 35 RESETL 36 COL 37 MDO 38 MDIO 39 VDD 40 Figure 4-1 Pin Configuration for XRCII P/N:PM0427 MX98745 3 MX98745 120 VDD 119 SIGDET3 118 RSCLK3 117 TDAT24 116 TDAT23 115 TDAT22 114 TDAT21 113 TDAT20 112 VDD 111 RDAT24 110 RDAT23 109 ...
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... LSCLK. TDAT4 is the Most Significant Bit. I, Local Synchrnous Clock. This pin supplies the frequency reference to TTL the MX98745 within same HUB. It should be driven by a crystal- controlled 25M clock source. I, Receive Data. These 5 bit parallel data symbol from transceiver are TTL latched by the rising edge of RSCLK of each port ...
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... EDAT and perform corresponding activity within XRCII itself. Expansion Data Activity. When XRCII detects that EDENL is asserted by external arbitor, it will assert EDACT high. System application can use this signal to control the data bus flow of EDAT. 5 MX98745 REV. 1.4, JUL. 8, 1998 ...
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... XRCII and indicates that there is collision on the receiving port. Transmit Clock. 25M Hz clock. TXD[3:0], TXEN, TXER are synchronous to this clock's rising edge. In PCS type MII (PMSEL is 1), CRS and COL are also synchronous to this clock's rising edge. 6 MX98745 REV. 1.4, JUL. 8, 1998 ...
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... When this pin is set to 1. Each port's scrambler/descrambler is controller by corre sponding bit in register #17. Internally pullup. Reset. Active Low. Will be filtered by LSCLK within the MX98745. Internal Bus Monitor. In house debugging usage. Internally pull down. 7 MX98745 ...
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... Collision Rate LED 0/EEPROM Clock/Partition Select. Value on this pin will be latched by MX98745 at the rising edge of RESETL as the value of Partition Select (PARSEL). When EECONF is set to 1, this pin will work as EEPROM clock pin and output by MX98745 after power on reset. When EEPROM operation is enabled, internal repeater function will be disabled until contents in EEPROM is loaded into MX98745 ...
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... LDS[2:0]. LED 6/Physical Address 3. Value on LED6 will be latched at the rising edge of RESETL as the physical address 3 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 6's Receivee/ Link, Partition, Isolation status and indicates 60% Network utilization and 15% collision rate according to the value on LDS[2:0] ...
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... P/N:PM0427 Description LED 7/Physical Address 4. Value on LED7 will be latched at the rising edge of RESETL as the physical address 4 of MX98745. If EECONF is set, Physical address will be overwritten by the value from EEPROM. After EEPROM operation is completed, this pin will display port 7's Receivee/ Link, Partition, Isolation status and indicates 80+% Network utilization and 20+% collision rate according to the value on LDS[2:0] ...
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... Figure 6-2 TX/MII Mixed Mode operation for XRC II P/N:PM0427 EEPROM Arb XRC DT& DT& PMD PMD Port 7 Port 8 Figure 6-1 Pure TX Mode operation for XRC II Arbitor XRC DT& DT& PMD PMD Port 7 Port 8 11 MX98745 XRC DT& PMD Port 15 DT& PMD Port 15 REV. 1.4, JUL. 8, 1998 ...
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... PHY address of each device is distinct. Register 0 and 1 are Command and Status registers which specified in [1]. Additional registers provided by MX98745 is located from address (decimal value). Port Control Registers are located from address #16 to address #20. These control registers include port A. Command Register (register #0) (R/W) ...
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... Forced to 0. Forced All ports are link up Any port is link fail. Will be set to 1 after this port is read Jabber condition in any port is detected Jabber condition detected for all ports Forced to 1. Table 6-2 Status Register Bit Definition 13 MX98745 R R ...
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... ResetP2 16.1 ResetP1 16.0 ResetP0 Each bit will not clear to 0 automatically whenever it is set ensure the MX98745 works properly, one should write 0 back to Port reset register after written 1 to corresponding bit. P/N:PM0427 Description Ignored when read reset Port 7's Logic not reset Port 7's Logic. ...
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... Enable Scrambler/Descrambler at Port Disable Scrambler/Descrambler at Port 2 The default value after power Enable Scrambler/Descrambler at Port Disable Scrambler/Descrambler at Port 1 The default value after power Enable Scrambler/Descrambler at Port Disable Scrambler/Descrambler at Port 0 The default value after power MX98745 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REV ...
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... Enable RX/TX functions at Port Disable RX/TX functions at Port 2. The default value after power Enable RX/TX functions at Port Disable RX/TX functions at Port 1. The default value after power Enable RX/TX functions at Port Disable RX/TX functions at Port 0. The default value after power MX98745 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REV ...
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... Port 2 Isolation function is not disabled. The default value is 0 after reset Port 1 Isolation function is disabled 0 : Port 1 Isolation function is not disabled. The default value is 0 after reset Port 0 Isolation function is disabled 0 : Port 0 Isolation function is not disabled. The default value is 0 after reset. 17 MX98745 R/W R/W R/W R/W R/W R/W R/W R/W ...
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... Port 2 Partition function is not disabled. The default value is 0 after reset Port 1 Parition function is disbled Port 1 Partition function is not disabled. The default value is 0 after reset Port 0 Parition function is disbled Port 0 Partition function is not disabled. The default value is 0 after reset. 18 MX98745 R/W R/W R/W R/W R/W R/W R/W R/W ...
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... Status is updated at every LSCLK clock Link Status port Link Status is Fail at Port 1 Status is updated at every LSCLK clock Link Status port Link Status is Fail at Port 0 Status is updated at every LSCLK clock. Table 6-8 Link Status Register Bit Definition 19 MX98745 R ...
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... Port 2 has been partitioned 0 : Port 2 has not been partitioned Status is updated every 40 ns Port 1 has been partitioned 0 : Port 1 has not been partitioned Status is updated every 40 ns Port 0 has been partitioned 0 : Port 0 has not been partitioned Status is updated every 40 ns. 20 MX98745 R REV ...
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... Clear to 0 after read Elastic Buffer Over/Underflow at Port Normal Condition. Clear to 0 after read Elastic Buffer Over/Underflow at Port Normal Condition. Clear to 0 after read Elastic Buffer Over/Underflow at Port Normal Condition. Clear to 0 after read. 21 MX98745 R ...
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... No Jabber condition at Port Receive Jabber Active at Port Jabber condition at Port Receive Jabber Active at Port Jabber condition at Port Receive Jabber Active at Port Jabber condition at Port 0 Table 6-11 Jabber Status Register Bit Definition 22 MX98745 R ...
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... Port Isolation is not occuring at port Port Isolation is occuring at port Port Isolation is not occuring at port Port Isolation is occuring at port Port Isolation is not occuring at port Port Isolation is occuring at port Port Isolation is not occuring at port 0. 23 MX98745 R ...
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... EECF Power on reset value of LDS0. After power on reset, Write 1 to this bit will not make EEPROM operation. When EECF is low, then value on corresponding pins (known as hardwire setting) will be latched by MX98745 and overwrite the default setting of MX98745. 31.10 Reserved Force to High all the time. ...
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... DC Output Voltage (Vout) Storage Temperature Range (TSTG) Power Dissipation (PD) ESD rating (Rzap = 1.5K, Czap = 100pF) Table 7-1 Absolute Maximum Rating for MX98745 Notice : Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cauase permanent damage to the device. This is a stress rating only and functional ...
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... CONDITIONS X1 = 25MHz VIN = Switching X1 = 25MHz VIN=VCC/GND X1=Undriven GND = 0V VI=VCC/GND Ioh = -2mA/ -4mA/ -8mA Iol = 2mA/ 4mA/ 8mA VOUT=VCC/ GND Ioh = -20uA Iol = 20uA Input Voltage Input Voltage VI=VCC/GND Table 8-1 DC Characteristics for MX98745 26 MX98745 MIN. MAX. UNIT - 150 600 uA - 0.8 V 2.0 VCC+0 ...
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... Low Time for MDC T04 MDIO Setup to MDC rising edge (sourced by STA) T05a MDIO Hold to MDC rising edge (sourced by STA) T05b MDIO Hold to MDC rising edge (source by XRC) P/N:PM0427 T01 T03 T04 T05 27 MX98745 MIN. MAX. UNIT 400 - ns 160 - ns 160 - ns 10 ...
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... The hold time of an MII signal relative to an MII clock edge is defined as the length of time between when the clock exits the switching region and when the signal enters the switching region. P/N:PM0427 T11 T13 T14 T15 28 MX98745 MIN. MAX. UNIT ...
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... Note 1 : The accurate TXCLK frequency shall be 25 MHz +/- 50 ppm. In PCS type MII, this signal is outputed by MX9745. In MAC type MII, this sig- nal is input to MX98745. Note 2 : The setup time of an MII signal relative to an MII clock edge is defined as the length of time be- ...
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... RSCLK Pulse Width High T43 RSCLK Pulse Width Low Time T44 RDAT[4:0] Valid to RSCLK Rise T45 RSCLK Rise to RDAT[4:0] Invalid Note 1 : The accurate RSCLK frequency shall be 25 MHz +/- 50 ppm. P/N:PM0427 T31 T41 T43 T45 30 MX98745 MIN. MAX. UNIT MIN. MAX. UNIT ...
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... Note 2 : Expansion port data will be released onto EDAT[4:0] at the next LSCLK rising edge right after EDACT is asserted which is not shown in this figure. Note 3 : ANYACT has not any timing relationship to LSCLK in MX98745. i. asynchronous to LSCLK. P/N:PM0427 T51 Figure 9-6 Timing Constraint RESEL T72 ...
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... Collision Condition to JAMI asserted (Note 2) T83 JAMO asserted to JAMI asserted (Note 3) Note 1 : EDENL2 asserted after collision will not make EDACT2 assert in MX98745 due to MX98745 will mask activity from expansion port from ces sation of collision to cessation of ANYACT2. Note 2 : Deassert timing is the same Note 3 : Deassert timing is the same ...
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... EPCLK EDAT Symbol Description T91 EPCLK to EDAT delay time (EPCLK and EDAT outputed from MX98745) T92 EDAT Setup Time (Input to MX98745) T93 EDAT Hold Time (Input to MX98745) D. LED Display LEDEN LDS2_0 LED7_0 Symbol Description T96 LEDEN Period T97 LDS2_0 Setup Time ...
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... PACKAGE INFORMATION 160-PIN PLASTIC QUAD FLAT PACK P/N:PM0427 MX98745 34 REV. 1.4, JUL. 8, 1998 ...
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... 10, 11:Change scale for utilization and collision rate LED display. 1.2 P28:Change configuration register (register #31) description. 1.3 P30:Change 7.0 ABSOLUTE MAXIMUM RATINGS:Power Dissipation, from 1500mw to 750mw. P30:Change 8.0 DC Characteristics:ICC(MAX.), form 300mA to 150mA. 1.4 P2:Change expansion port signal name from EPCLK to ANYACT. P/N:PM0427 MX98745 35 Date JAN. 31, 1997 MAR. 12, 1997 JUL. 03, 1997 JUL. 10, 1998 REV. 1.4, JUL. 8, 1998 ...
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... TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 36 MX98745 ...