mx98713 Macronix International Co., mx98713 Datasheet
mx98713
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mx98713 Summary of contents
Page 1
... MicroWire interface to external serial EEPROM which may contain Ethernet address, PCI vendor & device ID and other data P/N:PM0386 PMAC 100/10BASE PCI MAC CONTROLLER 1 INDEX MX98713 REV. 1.1, NOV. 8, 1996 ...
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... GENERAL DESCRIPTION The MX98713 PCI MAC ( PMAC ) device is an IEEE 802.3u Media Access Controller dedicated for PCI interface and is designed to ease interfacing with CSMA/CD type local area networks, including 100Mbps-TX/FX/T4 Fast Ethernet, 10Mbps Thick Ethernet, Thin Ehternet and StarLAN with external network transceivers and 10Mbps Twisted-pair Ethernet without external transceiver ...
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... ROM ROM port port TX RX FIFO FIFO PCS Scrambler Descrambler MII/SYM interface Fig. 1-- MX98713 PMAC Architecture And Interface Overview Board Ctrl Signals Board Ctrl port PCI BIU NWAY CTRL & REGS 10Mbps TP TRX interface PCI bus 3 INDEX MX98713 PCI Masters ...
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... TXLED RXLED 151 152 GDLED BPSEL2 153 LPBKB 154 155 BPSEL1 BPA15 156 157 CONF2 10/100 158 CONF1 159 TMS 160 MX98713 160 Pin PQFP 4 INDEX MX98713 80 BPA11 79 BPA12 78 BPA13 77 BPA14 76 AD0 75 AD1 74 VSS 73 AD2 72 AD3 71 VDD 70 AD4 69 AD5 68 VSS ...
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... PCI slave device select: asserted by the target of the current bus access. DEVSEL# I/O When the MX98713 is the initiator of current bus access, the target must assert DEVSEL# within 5 bus cycles; otherwise, the cycle will be aborted. PCI initialization device select: target specific device select signal for ...
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... PHY device external loopback control : driven by the MX98713 to force LPBKB O PHY device to do loopback. Boot PROM size select bit 2 : together with BPSEL1 to inform the MX98713 BPSEL2 I the memory size of boot PROM, 00 indicates 8K Byte, 01 indicates 16K Byte, 10 indicates 32K Byte and 11 indicates 64K Byte. ...
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... Pin Name TYPE Boot PROM address lines: driven by the MX98713, together with BPA15 to BPA[14:0] O access external boot PROM in size up to 64KByte. MDC O MII management interface clock: sourced by the MX98713 MDIO I/O MII management interface IO data bit EECS O Net ID ROM chip select EECK ...
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... PCS mode. TXEN O Transmit enable signal of MII/SYM interface BPD[7:0] I Boot PROM data lines: byte-wide data bus Twisted pair receive differential input: together with RXIM to provide 10BASE-T RXIP I differential receive input. Function and Driver Description 8 INDEX MX98713 ...
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... Serial mode select: Reserved for test, connected to Vdd for normal operation. BPSCR I Bypass Scrambler mode: Reserved for test; ground this pin for normal operation. TMS I NWAY test mode select: Reserved for test, connected to Vdd for normal operation. TEST I TEST pin: must be grounded. Function and Driver Description 9 INDEX MX98713 ...
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... Base address 3 (not used) 24-27h Base address 4 (not used) 28-2Bh Reserved 2C-2Fh Reserved 30-33h Expansion ROM base address 34-37h Reserved 38-3Bh Reserved 3Ch Interrupt line 3Dh Interrupt pin 3Eh Min_Gnt 3Fh Max_Lat 40h Driver area for the driver's special usage MX98713 10 INDEX ...
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... ID, then internal preset value of "10D9" is used by PMAC instead; otherwise, both 3Dh and 3Eh are loaded from serial PROM. When location 3Eh contains "FFFF", device ID is internally preset to "0512" for the MX98713. 5.1.3. PCI CCOMMAND AND STATUS RREGISTER ( PFCS ) PFCS Register ( 07h-04h) ...
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... Step Number, fixed to 0h and incremented for subsequent steps of the version. bit 7 - bit 4 : Revision Number, fixed to 0h and is incremented for subsequent revisions. bit 15 - bit 8 : not used bit 23 - bit 16 : Subclass, fixed to 0h. bit 31 - bit 24 : Base Class, fixed to 2h. MX98713 12 INDEX ...
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... PBIO Register ( 13h-10h) Configuration Base IO Address IO/Memory Space Indicator bit 0 : IO/Memory Space Indicator, fixed to 1 will map into the IO space. This is a read only field. bit 6 - bit 1 : not used. bit 31 - bit 7 : Defines the address assignment mapping of PMAC CSR registers. MX98713 13 INDEX ...
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... Expansion ROM Base Address Address Decode Enable bit 0 : Address Decode Enable, decoding will be enabled when both enable bit in PFCS<1>, and this expansion ROM register bit is 1. bit 10 - bit 1 : not used. bit 31 - bit 11 : Defines the 21 bits of expansion ROM base address. MX98713 14 INDEX ...
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... PCI DRIVER AREA REGISTER ( PFDA ) PFDA Register (40h) Driver Special Use bit 7 - bit 0 : not used. bit 15 - bit 8 : driver is free to read and write this field for any driver special purpose. bit 31 - bit 16 : not used. MX98713 15 INDEX ...
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... CSR10 reserved CSR11 General-purpose timer CSR12 General-purpose port CSR13 reserved CSR14 reserved CSR15 Watchdog timer CSR16 Test Operation Register ------------------------------------------------------------------------------------------------------------------------------------------- MX98713 Offset from CSR Base Address ( PBIO and PBMA ) 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h ...
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... CAL Cache Alignment, programmable address boundaries of data burst stop, PMAC can handle non-cache-aligned fragment as well as cache-aligned fragment efficiently. 18:17 TAP Transmit Auto-Polling time interval, defines the time interval for PMAC to performs transmit polling command automatically at transmit suspended state. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 0 17 INDEX ...
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... TRANSMIT POLL COMMAND ( CSR1 ) Transmit Poll command Value after reset is "FFF80000"h ------------------------------------------------------------------------------------------------------------------------------------------------ Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------------ 31:0 TPC Write only, when written with any value, PMAC will read transmit descriptor list in host memory pointed by CSR4 and then process the list. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 18 INDEX ...
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... Write only, when written with any value, PMAC reads receive descriptor list in host memory pointed by CSR4 and processes the list. ------------------------------------------------------------------------------------------------------------------------------------------------ 5.2.4. DESCRIPTOR LIST ADDRESS ( CSR3, CSR4 ) CSR3 for Receive List Base Address Start of Receive List Address Value after reset is unpredictable. MX98713 19 INDEX ...
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... FBE- Fatal Bit Error GTE- General Purpose Timer Expired RWT-Receive Watchdog Timeout RPS- Receive Process Stopped RU- Receive Buffer Unavailable RI- Receive Interrupt UNF- Transmit Underflow TJT- Transmit Jabber Timeout TU- Transmit Buffer Unavailable TPS- Transmit Process Stopped TI- Transmit Interrupt Value after reset is "FC005410"h MX98713 20 INDEX ...
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... Transmit Process Stopped Transmit Interrupt. indicating a frame transmission was completed. ------------------------------------------------------------------------------------------------------------------------------------------------ Table 2 -- Fatal Bus Error Bits ------------------------------------------------------------------------------------------------------------------------------------------------ CSR5<25:23> Process State ------------------------------------------------------------------------------------------------------------------------------------------------ 000 parity error for either SERR# or PERR#, cleared by software reset. 001 master abort 010 target abort 011 reserved 1XX reserved ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 21 INDEX ...
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... Waiting for receive packet 100 Suspended, receive buffer unavailable 101 closing receive descriptor 110 Purging the current frame from the receive FIFO due to unavailable receive buffer 111 queuing the receive frame from the receive FIFO into host receive buffer ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 22 INDEX ...
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... Threshold Control Bits, these bits control the selected threshold level for PMAC's transmit FIFO; transmission starts when frame size within the transmit FIFO is larger than the selected threshold. Full frames with a length less than the threshold are also transmitted. MX98713 ...
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... If CSR6<2> is reset, then physical addresses are perfect address filtered, according to a single physical address as specified in setup frame. ------------------------------------------------------------------------------------------------------------------------------------------------ Table 5 -- Transmit Threshold ------------------------------------------------------------------------------------------------------------------------------------------------ CSR6<21> CSR6<15:14> ------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------ CSR6<22>=0 CSR6<22>=1 (Threshold bytes) 128 72 256 96 512 128 1024 160 ( Store and Forward ) 24 INDEX MX98713 ...
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... MII/SYM 100Mbps 0 16 perfect filtering 1 512-bit hash + 1 perfect filtering 1 512-bit hash for multicast and physical addresses 0 Inverse filtering X Promiscuous 1 Promiscuous X Pass All Multicast 1 Pass All Multicast 25 MX98713 Function 10 Base MII 100MB/s MII PCS for 100Base-FX PCS and SCR for 100Base-TX INDEX ...
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... Transmit Jabber Timeout Enable, set together with CSR7<15> enables CSR5<3> Transmit Buffer Unavailable Enable, set together with CSR7<16> enables CSR5<2> Transmit Stop Enable, set together with CSR7<15> enables CSR5<1> Transmit Interrupt Enable, set together with CSR7<16> enables CSR5<0>. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 26 INDEX ...
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... Missed Frame Counter Value after reset is "FFFE0000"h ------------------------------------------------------------------------------------------------------------------------------------------------ Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------------ 16 MFO Missed Frame Overflow, set when missed frame counter overflow, reset when CSR8 is read. 15:0 MFC Missed Frame Counter, indicates the number of frames discarded because no host receive descriptor was available. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 27 INDEX ...
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... SRO When set together with SSR(CSR9<11>), the MX98713 performs a read cycle from the serial ROM. When set and SSR is reset, the MX98713 performs a write cycle to PHY. 13 SWO When set together with SSR, the MX98713 executes a write cycle to the serial ROM. When set and SSR is reset, the MX98713 executes a write cycle to the PHY ...
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... Timer value after reset is "FFFE0000"H. ------------------------------------------------------------------------------------------------------------------------------------------------ Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------------ 16 CON When set,the general purpose timer is in continuous operating mode. When reset, the timer is in one-shot mode. 15:0 Timer Value contains the timer value in a cycle time of 204.8us. ------------------------------------------------------------------------------------------------------------------------------------------------ Write Read Value yes - 0 yes - 1 - yes - 29 INDEX MX98713 ...
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... When GPC is reset any host read access to CSR12<7:0> reflects the input values on any pins defined as input pins and output values on any pins defined as output pins. The application of the general-purpose pins in board design should be correlated with the way the port driver software is using it. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 INDEX ...
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... When set the transmit channel is relased immediately after the jabber expiration. When reset the jabber is released 365ms to 420ms after jabber expiration for 10Mbps port. When reset the jabber is released 36.5ms to 42ms after the jabber expiration for 100Mbps port. 0 JBD Jabber Disable, set to disable transmit jabber function. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 31 INDEX ...
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... Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------------ 22 ErInt Set to 1 will enable early interrupt assertion before end of current packet receiving or transmission. PMAC will determine a good time to assert interrupt depending on the size of current packet. Others Reserved bits must be preserved as initialized value by MXIC's driver. ------------------------------------------------------------------------------------------------------------------------------------------------ MX98713 32 INDEX ...