88e1118r Marvell Semiconductor, Inc., 88e1118r Datasheet - Page 10

• Manufacturer Part Number: 88e1118r
• Description: Gigabit Ethernet Transceiver
• Manufacturer: Marvell Semiconductor, Inc.

Table 6:
64 -QFN
Pin #
64
1
2
3
4
38
39
10
57
Doc. No. MV-S105538-00, Rev. --
Page 10
Clock/Configuration/Reset/I/O
P i n N a m e
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
CLK125
XTAL_IN
XTAL_OUT
RESETn
VREF
Alaska
Gigabit Ethernet Transceiver
Typ e
I
0
I
®
P i n
I
I
I
I
O
I
88E1118R Technical Product Brief
Document Classification: Proprietary Information
D escr ip tio n
Hardware Configuration
Hardware Configuration
Hardware Configuration
Hardware Configuration
125 MHz Clock Output. When Hardware reset is asserted, a 25 MHz clock is
generated output, otherwise a 125 MHz clock is output.
Reference Clock. 25 MHz ± 50 ppm tolerance crystal reference or oscillator
input.
NOTE: If AVDDC is tied to 1.8V, then the XTAL_IN pin is not 2.5V/3.3V tolerant.
Reference Clock. 25 MHz ± 50 ppm tolerance crystal reference. When the
XTAL_OUT pin is not connected, it should be left floating.
Hardware reset. Active low.
0 = Reset
1 = Normal
RGMII input voltage reference.
Must be set to VDDOR/2 when used as 1.8V HSTL, 2.5V SSTL_2, and 3.3V.
Set to VDDOR when used as 2.5V LV CMOS.
If AVDDC is tied to 2.5V, then the XTAL_IN pin is not 3.3V tolerant.
Copyright © 2011 Marvell
May 6, 2011, Advance