v54c365324v ETC-unknow, v54c365324v Datasheet - Page 4

• Manufacturer Part Number: v54c365324v
• Description: 200/183/166/143 Volt Ultra High Performance Sdram Banks 512kbit
• Manufacturer: ETC-unknow

M O S E L V I T E L I C
Signal Pin Description
V54C365324V Rev. 1.2 August 2001
Pin
CLK
CKE
CS
RAS
CAS
WE
A
BA
DQ
DQMi
VDD/VSS
VDDQ/VSSQ
NC
0
-A
0
0
, BA
-DQ
10
1
31
Name
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address
Bank Select
Data Input/Output
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
Input Function
System clock input. Active on the positive rising edge to sample all inputs
Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self re-
fresh mode
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi
Latches row addresses on the positive edge of CLK with RAS low. En-
ables row access & precharge
Latches column addresses on the positive edge of CLK with CAS low.
Enables column access
Enables write operation
During a bank activate command, A
During a read or write command, A
addition to the column address A
define the bank to be precharged. A
during a precharge cycle, If A
is low, the BA0, BA1 is used to decide which bank to precharge
Selects which bank to activate.
Data inputs/output are multiplexed on the same pins
Makes data output Hi-Z. Blocks data input when DQM is active
Power Supply. +3.3V ± 0.3V/ground
Provides isolated power/ground to DQs for improved noise immunity
4
10
is high, all bank will be precharged, if A
10
0
is used to invoke auto precharge BA
10
0
-A
-A
is low, auto precharge is disabled
7
10
defines the column address. In
defines the row address.
V54C365324V
10