FS6108 American Microsystems, Inc., FS6108 Datasheet

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FS6108

Manufacturer Part Number
FS6108
Description
Zero Delay Buffer ic
Manufacturer
American Microsystems, Inc.
Datasheet
ISO9001
ISO9001
ISO9001
ISO9001
1.0
Table 1: Clock Enable Configuration
Table 2: Pin Descriptions
Key: DI = Digital Input; DI
DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground; # = Active-low pin
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
4, 13
5, 12
PIN
8, 9
14
15
10
11
16
S2
CONTROL
2
3
6
7
1
0
0
1
1
Generates up to nine clock outputs, grouped as 4-4-1
from one reference clock input
Pin enable/disable of two banks of four clocks
Auto power-down shuts off PLL, brings outputs low in
the absence of any REF input
Tracking skew < 200ps (spread-spectrum tolerant)
Input-to-output propagation delay < 200ps
Available in a 16-pin 0.150” SOIC
TYPE
DO
DO
DO
DO
DO
DO
DO
DO
DO
Features
DI
DI
P
P
S1
0
1
0
1
D
U
D
D
D
D
D
D
D
D
D
U
CLK_FB
CLK_A1
CLK_A2
CLK_A3
CLK_A4
CLK_B1
CLK_B2
CLK_B3
CLK_B4
CLK_A1:4
NAME
S2, S1
= Input with Internal Pull-Up; DI
Tristate
REF
VDD
VSS
Driven
Driven
Driven
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output that also provides an in-
ternal feedback connection to the PLL
Reference clock input
Two select inputs that enable and dis-
able the clock outputs, and enable or
bypass the PLL
3.3V power supply
Ground
CLOCK OUTPUTS (MHz)
CLK_B1:4
Tristate
Tristate
Driven
Driven
DESCRIPTION
D
= Input with Internal Pull-Down;
CLK_FB
Driven
Driven
Driven
Driven
Bank A
Bank B
Source
REF
PLL
PLL
PLL
Figure 1: Block Diagram
Figure 2: Pin Configuration
REF
S2
S1
CLK_A1
CLK_A2
CLK_B1
CLK_B2
FS6108
VDD
REF
VSS
S2
Control
1
2
3
4
5
6
7
8
PLL
1:9 Zero Delay Buffer IC
1:9 Zero Delay Buffer IC
1:9 Zero Delay Buffer IC
1:9 Zero Delay Buffer IC
FS6108
FS6108
FS6108
FS6108
16
15
14
13
12
11
10
9
CLK_FB
CLK_A4
CLK_A3
VDD
VSS
CLK_B4
CLK_B3
S1
VDD
CLK_FB
CLK_A1
CLK_A2
CLK_A3
CLK_A4
VSS
VDD
CLK_B1
CLK_B2
CLK_B3
CLK_B4
VSS
-01
-01
-01
-01
3.4.02

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FS6108 Summary of contents

Page 1

... Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC VDD CLK_FB CLK_A1 CLK_A2 PLL CLK_A3 CLK_A4 VSS Control VDD CLK_B1 CLK_B2 CLK_B3 CLK_B4 FS6108 VSS REF 1 16 CLK_FB CLK_A1 2 15 CLK_A4 CLK_A2 3 14 CLK_A3 VDD 4 13 VDD VSS ...

Page 2

... FS6108 FS6108 FS6108 FS6108 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 2.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied ...

Page 3

... REF to CLK_FB Φ t Measured @ 0.8V – 2.0V; C =30pF Measured @ 2.0V – 0.8V; C =30pF FS6108-01 FS6108-01 FS6108-01 FS6108-01 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 3 from typical. Negative currents indicate current flows out of the device. MIN. TYP 2 ...

Page 4

... FS6108 FS6108 FS6108 FS6108 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 3.0 Package Information Table 7: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1 ...

Page 5

... TEMPERATURE RANGE 16-pin (0.150”) SOIC (Commercial) 16-pin (0.150”) SOIC (Commercial) E-mail: tgp@amis.com 5 FS6108-01 FS6108-01 FS6108-01 FS6108-01 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC 1:9 Zero Delay Buffer IC OPERATING SHIPPING CONFIGURATION Tape and Reel Tubes 3.4.02 ...

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