SCH-V SHARP [Sharp Electrionic Components], SCH-V Datasheet
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SCH-V Summary of contents
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... LH28F008SC-V/SCH-V DESCRIPTION The LH28F008SC-V/SCH-V flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards ...
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... RY/BY GND GND (FBGA048-P-0608 LH28F008SC-V/SCH-V TOP VIEW CE ...
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... BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER DQ - OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 16 64 k-BYTE BLOCKS - 3 - LH28F008SC-V/SCH-V I LOGIC CE# WE# COMMAND USER INTERFACE OE# RP# RY/BY# WRITE V STATE PP PROGRAM/ERASE MACHINE VOLTAGE SWITCH V CC GND ...
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... HH ≤ RP# ≤ V produce spurious results and should not be attempted. HH (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results PP ≤ LH28F008SC-V/SCH-V enables setting of the HH ≤ memory PP PPLK , all write attempts to the flash memory LKO voltage (see Section 6.2.3 "DC ...
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... This datasheet contains LH28F008SC-V/SCH-V specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SC-V/ SCH-V flash memories documentation also includes ordering information which is referenced in Section 7. 1.1 New Features LH28F008SC-V/SCH-V Smart 5 flash memories ...
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... The access time the V AVQV voltage range of 4.75 to 5.25 V over the temperature range +70˚C (LH28F008SC-V)/ –25 to +85˚C (LH28F008SCH-V). At 4 the access time 120 ns. CC The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching) ...
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... The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read - 7 - LH28F008SC-V/SCH-V power supply PP . The device PPH1/2 either ...
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... SHARP allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. is required PHQV - 8 - LH28F008SC-V/SCH-V is required PHWL ) before another IH s flash memories ’ ...
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... Placing V successful block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Block LH28F008SC-V/SCH-V , the CUI additionally controls block voltage ≤ read operations PPLK on V enables PPH1/2 ...
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... Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when V voltages. V PPH1/2 PPH1/2 lock-bit configuration with V spurious results and should not be attempted. 7. Refer to Table 3 for valid D ’ 8. Don t use the timing both OE# and WE# are LH28F008SC-V/SCH-V ADDRESS V DQ RY/BY# 0 OUT X X ...
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... Clear Block Lock-Bits command can be done while RP Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. to enable LH28F008SC-V/SCH-V (NOTE 9) SECOND BUS CYCLE (NOTE 3) (NOTE 1) (NOTE 2) Data Oper ...
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... FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written LH28F008SC-V/SCH-V voltage. RP voltage. RP# can PP ...
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... At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte - 13 - LH28F008SC-V/SCH the absence of this PP PPH1/2 , status register bits SR.3 and SR.4 will ...
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... Fig. 7). The CPU can detect the completion of the set lock- bit event by analyzing the RY/BY# pin output or status register bit SR. LH28F008SC-V/SCH-V must remain at PP (the same V level used for byte write) PP ...
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... active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared LH28F008SC-V/SCH-V and clear block PP PPH1/2 ≤ PPLK ...
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... Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register LH28F008SC-V/SCH-V EFFECT BWSS DPS level ...
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... Command Sequence SR. Error 0 1 Block Erase SR.5 = Error 0 Block Erase Successful Fig. 3 Automated Block Erase Flowchart LH28F008SC-V/SCH-V BUS COMMAND COMMENTS OPERATION Data = 20H Write Erase Setup Addr = Within Block to be Erased Erase Data = D0H Write Confirm Addr = Within Block to be Erased ...
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... SR.1 = Device Protect Error 0 1 SR.4 = Byte Write Error 0 Byte Write Successful Fig. 4 Automated Byte Write Flowchart LH28F008SC-V/SCH-V BUS COMMAND COMMENTS OPERATION Setup Data = 40H Write Byte Write Addr = Location to be Written Data = Data to be Written Write Byte Write Addr = Location to be Written ...
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... Fig. 5 Block Erase Suspend/Resume Flowchart BUS COMMAND OPERATION Erase Write Suspend Read Standby Standby Erase Write Resume Read - 19 - LH28F008SC-V/SCH-V COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Block Erase Suspended 0 = Block Erase Completed Data = D0H Addr = X ...
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... Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Byte Write Resumed Array Data Fig. 6 Byte Write Suspend/Resume Flowchart LH28F008SC-V/SCH-V BUS COMMAND COMMENTS OPERATION Data = B0H Byte Write Write Addr = X Suspend Status Register Data Read Addr = X Check SR ...
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... Command Sequence SR. Error 0 1 Set Lock-Bit SR.4 = Error 0 Set Lock-Bit Successful Fig. 7 Set Block and Master Lock-Bit Flowchart LH28F008SC-V/SCH-V BUS COMMAND COMMENTS OPERATION Set Data = 60H Block/Master Write Addr = Block Address (Block), Lock-Bit Device Address (Master) Setup Set Data = 01H (Block), ...
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... Device Protect Error 0 1 Command Sequence SR. Error 0 1 Clear Block Lock-Bits SR.5 = Error 0 Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart LH28F008SC-V/SCH-V BUS COMMAND COMMENTS OPERATION Clear Block Data = 60H Write Lock-Bits Addr = X Setup Clear Block Data = D0H Write Lock-Bits ...
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... Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the System command sequence must be repeated after normal - 23 - LH28F008SC-V/SCH power supply PP CC supply traces and ...
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... RP# is first raised to V 6.2.4 through 6.2.6 "AC CHARACTERISTICS - READ-ONLY and WRITE OPERATIONS" and Fig. 12, Fig. 13 and Fig. 14 for more information. when V is LKO PP will inhibit LH28F008SC-V/SCH-V standby or sleep modes and t wake-up cycles PHQV PHWL . See Section IH ...
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... LH28F008SC-V During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F008SCH-V During Read, Block Erase, Byte Write and Lock-Bit Configuration ... –25 to +85°C Temperature under Bias ............. –25 to +85°C Storage Temperature ........................ –65 to +125°C Voltage On Any Pin , and RP#) .... – ...
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... TTL IH (Standard Testing Configuration) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 5.0±0. 5.0±0 NOTE : 1. Applied to high-speed products, LH28F008SC-V85 and LH28F008SCH-V85 OUT LH28F008SC-V/SCH-V UNIT CONDITION 0 0.0 V OUT 1.5 OUTPUT = 5.0±0. 2.0 OUTPUT 0.8 (0. for a Logic "0". Input timing ...
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... CE ±2 ±15 µ 200 µA 1 0.1 5 µ 200 µ LH28F008SC-V/SCH-V TEST CONDITIONS Max GND Max GND OUT CC CMOS Inputs Max. CC ...
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... RP erase, byte write, and lock-bit configuration operations are not guaranteed with V be attempted. (min.), between 9. RP# connection PPH1 (max.). maximum cumulative period of 80 hours. PPH2 to CCR - 28 - LH28F008SC-V/SCH-V TEST UNIT CONDITIONS Min ...
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... See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing after the falling Load Circuit" (Standard Configuration) for testing GLQV . characteristics LH28F008SC-V/SCH-V (NOTE 1) (NOTE 5) (NOTE 5) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 MIN. MAX. MIN. MAX. 90 120 90 120 90 120 400 400 45 50 ...
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... V IH WE# ( High Z DATA (D/Q) ( RP# ( Fig Waveform for Read Operations Device Data Valid Address Selection Address Stable t AVAV t ELQV t GLQV t GLQX t ELQX Valid Output t AVQV t PHQV - 30 - LH28F008SC-V/SCH-V t EHQZ t GHQZ t OH High Z ...
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... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 10 "Transient Input/Output Reference for block erase, Waveform" and Fig. 11 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F008SC-V/SCH-V (NOTE 6) (NOTE 6) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 MIN. MAX. MIN. MAX. 90 120 100 100 ...
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... Write Read Array command. Fig Waveform for WE#-Controlled Write Operations (NOTE 3) (NOTE AVAV AVWH WHAX t WHEH t WHGL t t WHWL WHQV1/2/3/4 t WLWH t DVWH t WHDX WHRL t PHHWH t VPWH - 32 - LH28F008SC-V/SCH-V (NOTE 5) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
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... Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 10 "Transient Input/Output Reference for block erase, Waveform" and Fig. 11 "Transient Equivalent Testing IN Load Circuit" (Standard Configuration) for testing characteristics LH28F008SC-V/SCH-V (NOTE 6) (NOTE 6) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 MIN. MAX. MIN. MAX. 90 120 100 100 ...
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... Read status register data. 6. Write Read Array command. Fig Waveform for CE#-Controlled Write Operations (NOTE 3) (NOTE AVEH EHAX t EHWH t EHGL t t EHEL EHQV1/2/3/4 t ELEH t DVEH t EHDX EHRL t PHHEH t VPEH - 34 - LH28F008SC-V/SCH-V (NOTE 5) (NOTE 6) Valid D IN SRD t QVPH t QVVL ...
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... NOTE , reset time RP# going high until outputs are valid. 4. When the device power-up, holding RP#-low minimum 100 ns is required after V range and also has been in stable there LH28F008SC-V/SCH 5.0±0 UNIT MIN. MAX. 100 ns 12 µs ...
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... C ˚ NOTE MIN. TYP. 2 6.5 2 0.4 2 0.9 2 9.5 2 0.9 3. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested LH28F008SC-V/SCH-V (NOTE 5.0±0 12.0±0 (NOTE 1) (NOTE 1) MAX. MIN. TYP. MAX. 8 TBD 4.8 6 TBD 0.5 TBD 0.3 0.4 TBD 1 ...
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... C = Smart 5 Technology Operating Temperature Blank = –25 to +85 C OPTION ORDER CODE 1 LH28F008SCXX-V85 2 LH28F008SCXX-V12 LH28F008SC-V/SCH-V Access Speed (ns (5.0 0.25 V (5.0 0.5 V 120 ns (5.0 0.5 V) Limited Voltage Option only CC Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend R = 40-pin TSOP (I) (TSOP040-P-1020) Reverse bend ...
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TSOP (TSOP040-P-1020 0.3 20.0 0.2 18.4 0.3 19.0 PACKAGING Package base plane ...
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SOP (SOP044-P-0600 0.4 0 0.1 0.15 M 1.27 TYP 0.2 28.2 PACKAGING 0.15 0.05 Package base plane ...
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CSP (FBGA048-P-0608) B 0.1 S TYP. 0.8 TYP. 0 0.1 S TYP. 0 0.2 8 TYP. 1.2 0.03 0. PACKAGING Land ...