SPI-4 ETC2 [List of Unclassifed Manufacturers], SPI-4 Datasheet - Page 2

• Manufacturer Part Number: SPI-4
• Description: Core w/ FIFOs V1.0 For Altera PLDs
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

SPI-4 Phase 1 Core V1.0
On the system side, the SPI-4 Phase 1 core
interfaces to a single or to multiple links or
ports via Altera’s Atlantic interface.
The Spi4Tx block monitors the Source
FIFOs fill level and the flow control
information received from the opposite side
of the SPI-4 interface. If a Source FIFO has
data and the flow control information for the
corresponding channel indicates that it is
ready to accept data, the Spi4Tx block
initiates a data transfer from the Source
FIFO towards the SPI-4 interface.
The Spi4Rx block transmits the Sink FIFO
status information to the opposite side
according to the Sink FIFO almost-full flags.
The Spi4Rx block stores data received for a
particular link in that link’s FIFO. Sink FIFO
flags indicate to the user the presence of
data in the FIFO(s).
Gate Count
The SPI-4 Phase 1 Core configured for 4
channels and targeted to APEX II uses:
Logic Elements (LEs): 2700
Embedded System Blocks (ESBs): 23
The above numbers include the core and a
small amount of circuitry to implement a
loopback on the Atlantic Interface.
Figure 2: SPI-4 Phase 1 Link Layer Application
Layer
PHY
Line Rx
Line Tx
SPI-4
Data
Data
I/F
Control
Spi4Rx
Spi4Tx
Spi4
FIFO(s)
FIFO(s)
Source
Sink
Status
Interface
Atlantic
Processor
Layer
Link
Design Package
The SPI-4 Phase 1 Core source code
package contains:
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Supported Tools
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Ordering Information
Modelware, Inc.
Tel: [phone]
Fax: [phone]
E-mail: [e-mail]
Internet: www.modelware.com
Trademarks
Modelware is a registered trademark of
Modelware, Inc.
Altera, Quartus, and Atlantic are trademarks
of Altera Corporation.
FlexBUS is a trademark of AMCC.
Source code or Netlist
Test bench (source code option)
Scripts and data files for simulation
(behavioral, gate-level, and back-
annotated), synthesis, and FPGA layout
Detailed documentation:
⇒ Reference Guide: Core features,
⇒ User's Guide: Core simulation,
MTI Modelsim for simulation
Exemplar Leonardo Spectrum for
synthesis
Altera Quartus
architecture, interfaces, and
operation
synthesis, and FPGA layout step-by
step procedures.
Product Brief
June 2001