em3027 EM Microelectronic, em3027 Datasheet - Page 12

• Manufacturer Part Number: em3027
• Description: Real-time Clock With I2c Or Spi Interface, Crystal Temperature Compensation, Battery Switchover And Trickle Charger
• Manufacturer: EM Microelectronic

Any serial communication with the chip starts with a “Transmission START” and terminates with the “Transmission STOP”.
“Transmission START”
At the same moment the “Transmission START” is detected a copy of Watch, Timer, and Temperature register content is
copied into a cache memory. A following read access is provided from the cache memory.
Data in the cache for reading are stable until the “Transmission STOP”.
At the same moment the “Transmission STOP” is detected, the content of the cache memory is copied into Watch, Timer, or
Temperature registers selected by the “page address” when R/W was set to ‘1’.
7.1
The I2C protocol is a bidirectional protocol using 2 wires
for master-slave communication. SCL (clock) and SDA
(data) signals are used. This protocol allows a
connection of more slaves through a bus. The bus is
pulled-up (externally by resistors) and drivers are
realised by open drain drivers. This chip can work as
slave only.
The communication is controlled by the master. At the
beginning of each transmission a start bit is sent
(transmission START). A slave address follows with last
bit which selects if READ or WRITE is initiated. If slave
address sent by the master is equal to the slave address
of the slave then slave continues to communicate with
the master. Each slave address, address or data byte is
finished by an acknowledge bit (ACK). It’s possible to
WRITE/READ the whole “page” during one transmission
I2C: Write transmission
S
I2C: Read transmission
S
S
ACKs
ACKm ...
R/W
P
Copyright © 2008, EM Microelectronic-Marin SA
07/08 – rev B
“Transmission STOP”
7
1010110
Address
1010110
Address
Slave
Serial communication
How to perform READ/WRITE through I2C
Slave
I2C
SPI
I2C
SPI
...
...
...
...
R
R/W
0
an acknowledge from the slave
an acknowledge from the master
read/write select
– START condition
– CS goes to active
– STOP condition
– CS goes to inactive
a start condition sent by a master
a stop condition
R/W
0
ACKs
ACKs
Address
Address
ACKs
ACKs
P
S
Data Byte
1010110
Address
(1)
Slave
12
with automatic address increment feature. Only three
less specified bits of the address are incremented.
In case of WRITE transmission the address byte is sent
to the slave and data bytes can follow (MSB first order is
used). A less significant part of the address is
incremented after each data byte is received. The “page
address” is fixed until a new address is received.
In case of READ transmission the slave sends data
bytes. An address is defined by the last address change
(WRITE transmission or a last increment). The “page
address” can be changed only by WRITE transmission. A
less significant part of the address is incremented also
after each ACK received from the master. If ACK is not
received then data are read from the same address.
At the end of each transmission a stop bit is send
(transmission STOP).
ACKs
R/W
1
ACKs
Data Byte
(n-1)
Data
byte
(1)
ACKs
ACKm
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EM3027
Data Byte
Data
byte
(n)
(n)
ACKm
ACKs
P
P