CS4329-KP CIRRUS [Cirrus Logic], CS4329-KP Datasheet
CS4329-KP
Related parts for CS4329-KP
CS4329-KP Summary of contents
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... The CS4329 also includes an extremely flexible serial port utilizing mode select pins to support multiple inter- face formats. The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments. ORDERING INFORMATION CS4329-KP CS4329-KS CDB4329 DIF2 DEM0 DEM1 VA ...
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... kHz Fs = 44.1 kHz kHz Normal Operation Power-down Normal Operation Power-down PSRR CS4329 = 20 k differential Min Typ Max - 103 - 101 106 - - 101 - - 104 - - ...
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... MCLK / LRCK = 512 MCLK / LRCK = 512 MCLK / LRCK = 384 MCLK / LRCK = 384 MCLK / LRCK = 256 MCLK / LRCK = 256 t sclkl t sclkh t sclkw t slrd t slrs t sdlrs t sdh SCLK / LRCK = 64 t sclkw t sdlrs t sdh t sdh CS4329 Min Typ Max 1.90 2.0 2. 100 Min Typ Max ...
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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4329 slrs t t sclkl slrd t sdh t sdlrs External Serial Mode Input Timing t t sdlrs sdh Internal Serial Mode Input Timing ...
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... (AGND = 0 V, all voltages with respect to ground.) Symbol Positive Analog VA Positive Digital VD | IND stg (DGND = 0V; all voltages with respect to ground) Symbol Positive Digital VD Positive Analog VA |VA - VD| CS4329 Min Typ Max Unit 2 0 ±10 Min Max Unit -0.3 6.0 V -0.3 6.0 V ...
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... AOUTL- 12 DIF2 CS4329 7 LRCK 9 AOUTL+ SCLK* 10 SDATA 1 DEM0 2 DEM1 AOUTR- 15 MUTE_R 16 MUTE_L 11 AUTO_MUTE AOUTR+ 8 MCLK DGND AGND SCLK must be connected to DGND for operation in Internal SCLK Mode Figure 1. Typical Connection Diagram CS4329 +5V Analog + Analog Conditioning 18 13 Analog Conditioning 14 DS153F1 ...
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... GENERAL DESCRIPTION The CS4329 is a complete stereo digital-to-analog system including 128× digital interpolation, fourth- order delta-sigma digital-to-analog conversion, 128× oversampled one-bit delta-sigma modulator and analog filtering. This architecture provides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate between 1 and 50 kHz, including the standard audio rates of 48, 44 ...
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... MCLK. Once the MCLK to LRCK fre- quency ratio has been detected, the phase and frequency relationship between the two clocks must remain fixed. If during any LRCK this rela- tionship is changed, the CS4329 will reset. Table 1 illustrates the standard audio sample rates and the required MCLK frequencies. Fs ...
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Left Channel LRCK SCLK SDATA Format 0 SDATA Format 1 SDATA Format 2 ...
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Left Channel LRCK SCLK SDATA 16-Bit SDATA 18-Bit SDATA ...
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... Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4329 supports both external and internal serial clock generation modes. External Serial Clock The CS4329 will enter the external serial clock mode more high\low transitions are detect the SCLK pin during any phase of the LRCK period ...
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... Vpp (2Vrms) differen- tial signal as shown in Figure 12 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (x Fs) Figure 9. CS4329 Combined Digital and Analog Filter Stopband Rejection 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.45 0.48 0.51 0.54 Frequency (x Fs) Figure 10. CS4329 Combined Digital and Analog ...
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... All mode pins which require VD should be connected to pin 6 of the CS4329. All mode pins which require DGND should be con- nected to pin 5 of the CS4329. Pins 4 and 5, AGND and DGND, should be connected together at the CS4329. DGND for the CS4329 should not be con- fused with the ground for the digital section of the system ...
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... Figure 19 shows the fade-to-noise linearity. The in- put signal is a dithered 20-bit 500 Hz sine wave which fades from -60 to -120 dBFS. During the fade, the output from the CS4329 is measured and compared to the ideal level. Notice the very close tracking of the output level to the ideal, even at low 14 level inputs ...
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... -120 14k 16k 18k 20k -60 -50 -40 -30 -20 dBFS Figure 15. THD+N vs. Amplitude 2.5k 5k 7.5k 10k 12.5k 15k Hz Figure 17. -20 dBFS FFT -100 -80 -60 -40 dBFS Figure 19. Fade-to-Noise Linearity CS4329 -10 +0 17.5k 20k - ...
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... Analog output connections for the Left channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. 16 PDIP and SSOP DEM0 DIF0 1 20 DEM1 DIF11 AOUTL AGND AOUTL DGND 5 16 MUTE_L MUTE_R LRCK AOUTR MCLK AOUTR SCLK DIF2 10 11 SDATA AUTO-MUTE CS4329 DS153F1 ...
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... Two's complement MSB-first serial data of either 16 bits is input on this pin. The data is clocked into the CS4329 via the SCLK clock and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0, DIF1 and DIF2 ...
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... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 18 CS4329 DS153F1 ...
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... SSOP PACKAGE DRAWING SIDE VIEW INCHES MIN MAX -- 0.084 0.002 0.010 0.064 0.074 0.009 0.015 0.272 0.295 0.291 0.323 0.197 0.220 0.022 0.030 0.025 0.041 0° 8° END VIEW L SEATING PLANE MILLIMETERS NOTE MIN MAX -- 2.13 0.05 0.25 1.62 1.88 0.22 0.38 2,3 6.90 7.50 7.40 8.20 5.00 5.60 0.55 0.75 0.63 1.03 0° 8° CS4329 ...
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... MIN MAX 0.000 0.210 0.015 0.025 0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.980 1.060 0.300 0.325 0.240 0.280 0.090 0.110 0.280 0.320 0.300 0.430 0.000 0.060 0.115 0.150 0° 15° CS4329 SIDE VIEW MILLIMETERS MIN MAX 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 24.89 26.92 7.62 8.26 6.10 7.11 2.29 2.79 7.11 8 ...
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... Analog outputs are provided via RCA connectors for both channels. The CS8412 digital audio receiver I.C. provides the sys- tem timing necessary to operate the CS4329/90 and will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be config- ured to accept external timing signals for operation in a user application during system development ...
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... Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. CS4329/90 Digital to Analog Converter A description of the CS4329 or CS4390 is included in the CS4329 and CS4390 data sheets. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 9 ...
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... CS8412) and placing J22 in the 1 position and J23 in the 0 position. Analog Filter The design of the second-order Butterworth low- pass filter, Figure 6, is discussed in the CS4329 and CS4390 data sheets and the applications note "De- sign Notes for a 2-pole Filter with Differential In- put." ...
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... CS4329/90 SCLK Mode DEM_8412 Selects source of de- emphasis control Notes Default setting from factory 24 input +5 Volts for the CS4329/90, CS8412 and digital section input input ground connection from power supply input digital audio interface input via coax input digital audio interface input via optical ...
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... LRCK SCLK CS8412 SDATA Digital Audio Interface Fig 9 De-emphasis Mode Fig 3 DS153DB3 I/O for Clocks and Data Fig 7 CS4329 or CS4390 Fig 2 Mute Calibration and Section Format Select Section Fig 4 Fig 5 Figure 1. System Block Diagram and Signal Flow CDB4329 CDB4390 AOUTL- AOUTL+ Analog ...
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... Figure 2. CS4329/90 and Connections ...
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Figure 5. Calibration and Format Select Circuitry DS153DB3 Figure 3. De-emphasis Circuitry Figure 4. Mute Circuitry CDB4329 CDB4390 27 ...
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NOTE: Rigth channel components in parentheses. 28 Figure 6. 2-pole Analog Filter Figure 7. I/O Interface for Clocks and DATA CDB4329 CDB4390 DS153DB3 ...
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OPTI Toshiba TORX173 optical receiver available from Insight Electronics DS153DB3 Figure 8. Digital Audio Input Circuit CDB4329 CDB4390 29 ...
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Note: U2 and U4 can not be installed simultaneously. Figure 9. CS8412 and Connections ...
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DS153DB3 Figure 10. Power Supply Connections CDB4329 CDB4390 31 ...
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Figure 11. CDB4329/90 Component Side Silkscreen 32 CDB4329 CDB4390 DS153DB3 ...
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DS153DB3 Figure 12. CDB4329/90 Component Side (top) CDB4329 CDB4390 33 ...
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Figure 13. CDB4329/90 Solder Side (bottom) CDB4329 CDB4390 DS153DB3 ...
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Notes • ...
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