CS4953-CL CIRRUS [Cirrus Logic], CS4953-CL Datasheet
CS4953-CL
Related parts for CS4953-CL
CS4953-CL Summary of contents
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... CCIR601 Master/Slave input modes l Stable color subcarrier for MPEG2 systems l NTSC closed caption encoder with interrupt l Supports Macrovision copy protection in CS4953 version l Host interface configurable for parallel or I compatible operation l General purpose input and output pins l Individual DAC power-down capability ...
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TABLE OF CONTENTS AC & DC PARAMETRIC SPECIFICATIONS .....................................................................4 INTRODUCTION ...............................................................................................................11 FUNCTIONAL DESCRIPTION .........................................................................................11 Video Timing Generator .........................................................................................11 Video Input Formatter .............................................................................................11 Color Subcarrier Synthesizer ..................................................................................12 Chroma Path ..........................................................................................................12 Luma Path ..............................................................................................................12 Digital to Analog Converters ...................................................................................13 Voltage Reference ..................................................................................................13 ...
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Subcarrier Synthesis Register ......................................................................... 33 Hue LSB Adjust Register ................................................................................. 33 Hue MSB Adjust Register ................................................................................ 33 Closed Caption Enable Register...................................................................... 34 Closed Caption Data Register ......................................................................... 34 Interrupt Enable Register ................................................................................. 34 Interrupt Clear Register.................................................................................... 35 Device ID Register ...
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AC & DC PARAMETRIC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS: Parameter Power Supply Input Current Per Pin Output Current Per Pin Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Warning: Operating beyond these limits may result in permanent damage to ...
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D.C. CHARACTERISTICS: Parameter Digital Inputs High Level Input Voltage HSYNC/VSYNC/FIELD/CLKIN High Level Input Voltage Low Level Input Voltage Input Leakage Current Digital Outputs High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Output Leakage Current Analog Outputs ...
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D.C. CHARACTERISTICS Parameter Static Performance DAC Resolution Differential Non-Linearity Integral Non-Linearity Dynamic Performance Differential Gain Differential Phase Signal to Noise Ratio Hue Accuracy Saturation Accuracy 6 (Continued) Symbol DNL INL DB DP SNR CS4952/53 Min Typ ...
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A.C. CHARACTERISTICS: Parameter Pixel Input and Control Port Clock Pulse High Time Clock Pulse Low Time Clock to Data Set-up Time Clock to Data Hold Time Clock to Data Output Delay CLK V[7:0] HSYNC*/VSYNC* (Inputs) HSYNC*/VSYNC*/ CB/FIELD/INT (Outputs) Figure 1. ...
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A.C. CHARACTERISTICS: Parameter 8-bit Parallel Host Interface Read Cycle Time Read Pulse Width Address Setup Time Read Address Hold Time Read Data Access Time Read Data Hold Time Write Recovery Time Write Pulse Width Write Data Setup Time Write Data ...
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A.C. CHARACTERISTICS: Parameter Reset Timing Reset Pulse Width RESET* DS223PP2 (Continued) Symbol T res T res Figure 4. Reset Timing CS4952/53 Min Typ Max Units 100 ns 9 ...
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... Pixel Data Figure 5. Typical Connection Diagram ( Ferrite Bead 4.7 µF 0.1 µ VAA 18 XTAL VREFOUT 19 ADDR 8 PDAT[7:0] CVBS75 31 RD* 32 WR* CVBS37 CS4952 35 SDA CS4953 36 SCL 33 CLK 8 V[7:0] 7-14 15 FIELD 16 HSYNC*/CB 17 VSYNC* RESET* 6 TEST GND CS4952/ VREFIN 0.1 µF ...
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INTRODUCTION The CS4952 complete multi-standard digital video encoder implemented in current 5-volt only CMOS technology. CCIR601 or CCIR656 compli- ant digital video input can be converted into NTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I, ...
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Color Subcarrier Synthesizer The subcarrier synthesizer is a digital frequency synthesizer that produces the correct subcarrier fre- quency for NTSC or PAL. The CS4952/3 generates the color burst frequency based on the input CLK (27 MHz). Color burst accuracy and ...
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Digital to Analog Converters The CS4952/3 provides four complete simulta- neous 27 MHz DACs for analog video output: one 9-bit for S-video chrominance, one 9-bit for S-Vid- eo luminance, and two 9-bit composite outputs. Both S-Video DACs are designed for ...
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OPERATIONAL DESCRIPTION Reset Hierarchy The CS4952/3 is equipped with an active low asyn- chronous reset input pin RESET. RESET is used to initialize the internal registers and the internal state machines for subsequent default operation. See the electrical and timing ...
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V [7:0] pins. Figure 7 illus- trates horizontal timing for CCIR601 input in Mas- ter Mode. Note that the CS4952/3 expects to receive the first active pixel data ...
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NTSC Vertical Timing (odd field) Line HSYNC* VSYNC* FIELD NTSC Vertical Timing (even field) Line HSYNC* VSYNC* FIELD PAL Vertical Timing (odd field) Line HSYNC* VSYNC* FIELD PAL Vertical Timing (even field) Line HSYNC* VSYNC* FIELD ...
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NTSC Interlaced The CS4952/3 supports NTSC-M and PAL-M modes where there are 525 total lines per frame and two fixed 262.5 line fields per frame and 30 total frames occuring per second. Please reference Fig- ure 9 for NTSC interlaced ...
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Burst Phase = 135 degrees relative to U ...
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VSYNC will transition low to begin field one and will remain low for 2.5 lines or (864 x 2.5) 2160 pixel cycles. Digital video input is expected to be delivered to the CS4952/3 V [7:0] pins for 287 lines beginning ...
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Burst Phase = 135 degrees relative to U Figure 11. PAL Video Non-Interlaced Progressive Scan Timing 20 VSYNC* Drops Analog Field 1 313 1 ...
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Burst begins with positive half-cycle Burst phase = reference phase = 180 relative to B-Y Figure 12. NTSC Video Non-Interlaced Progressive Scan Timing Composite ...
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NTSC-MC Address Register CIR601 0x00 CONTROL_0 0x01 CONTROL_1 0x10 SC_AMP 0x11 SC_SYNTH0 0x12 SC_SYNTH1 0x13 SC_SYNTH2 0x14 SC_SYNTH3 Table 2. Multi-standard Format Register Configurations Digital Video Input Modes The CS4952/3 provides 2 different digital video in- put modes that are ...
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System NTSC-M PAL- PAL-N (Argentina) PAL-M Table 3. Multi-standard Format FSC Register Configurations ±1350 Hz. It varies per television but in many cases given an MPEG-2 system clock of 27 MHz ±1350 Hz the resultant ...
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COLOR Cb White 0 Yellow -84 Cyan +28 Green -56 Magenta +56 Red -28 Blue +84 Black 0 Table 4. Internal Color Bar Values (8-bit values, Cb/Cr are in 2’s complement format) Interrupts In order to better support precise video ...
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VREF The CS4952/3 can operate with or without the aid of an external voltage reference. The CS4952/3 is designed with an internal voltage reference genera- tor that provides a VREFOUT signal. The internal voltage reference is utilized by electrically con- ...
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In this mode turn-on through the control register will not be instantaneous. CVBS75 DAC The CVBS75 pin is driven from a 9-bit 27 MHz current output DAC that internally receives a com- bined luma and chroma signal to ...
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PROGRAMMING Host Control Interface The CS4952/3 host control interface can be config- 2 ured for 8-bit parallel operation. The 2 CS4952/3 will default operation when the RD and WR pins are both tied low ...
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... Note that this table and the subsequent register description section describe the full register map for CS4952 only. A complete CS4953 register set description is only available to Macrovision ACP-PPV Licensed Buyers. Register Name Type CONTROL_0 r/w CONTROL_1 r/w ...
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Control Register 0 Address 0x00 Bit Number 7 6 Bit Name TV_FMT Default 0 0 Bit Mnemonic 7:5 TV_FMT selects the TV display format 000: 001: 010: 011: 100: 101: 110-111: 4 MSTR 1: Master Mode, 0: Slave Mode 3 ...
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Control Register 2 Address 0x02 Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic 7:4 - reserved Selects between 4.2 Mhz and 6 Mhz on-chip luminance low pass filters; default 3 Y_BW value is zero which selects the ...
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Status Register Address 0x07 Bit Number 7 6 Bit Name RESERVED Default 0 0 Bit Mnemonic 7:6 - reserved 5 CC_INT_21 Interrupt flag for line 21 (closed caption) complete 4 CC_INT_284 Interrupt flag for line 284 (closed caption) complete 3 ...
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GPIO Data Register Address 0x0A Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic GPIO data register; data is output on PDAT [7:0] bus if appropriate bit in 7:0 GPIO_DATA GPIO_CTRL_REG (0x09) is set to “1”; data on ...
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Subcarrier Amplitude Register Address 0x10 Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic 7:0 AMP Color burst amplitude Subcarrier Synthesis Register Address 0x11 0x12 0x13 0x14 Register Bits Mnemonic SC_SYNTH0 7:0 SC_SYNTH1 7:0 SC_SYNTH2 7:0 SC_SYNTH3 7:0 ...
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Closed Caption Enable Register Address 0x18 Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic 7:2 - reserved 1 EN_284 enable closed caption for line 284 0 EN_21 enable closed caption for line 21 Closed Caption Data Register ...
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... Address 0x3D Bit Number 7 6 Bit Name Default 0 0 Bit Mnemonic 7:4 DEV_ID 0000 device ID for CS4952 0001 device ID for CS4953 3:0 - These bits are reserved and the value they return on a read is not defined DS223PP2 INT_CLR Read/Write 5 4 RESERVED 0 0 Function ID_REG ...
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BOARD DESIGN & LAYOUT CONSIDERATIONS The printed circuit layout should be optimized for lowest noise on the CS4952/3 power and ground lines. Digital and analog sections should be physi- cally separated and the CS4952/3 placed as close to the output ...
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If microstrip techniques are used, split the analog and digital ground planes and use proper RF decoupling techniques. Analog Interconnect ...
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DEVICE PINOUT - 44 PLCC VAA GND VAA CVBS37 CVBS75 TEST FIELD HSYNC/CB VSYNC XTAL ADDR VAA GND GND CS4952/3-CL 11 ...
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PLCC Pin Description Pin Name Pin Number V [7:0] 14, 13, 12, 11, 10 CLK 33 ADDR 19 XTAL 18 HSYNC/CB 16 VSYNC 17 FIELD PDAT [7:0] 23,24,25,26,27,28,29,30 SDA 35 SCL 36 ...
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PLCC PACKAGE DRAWING DIM INCHES MIN MAX 0.165 0.180 4.043 0.090 0.120 2.205 0.013 0.021 0.319 0.685 0.695 16.783 0.650 0.656 15.925 0.590 0.630 ...
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DEVICE PINOUT - 44 TQFP VAA GND VAA CVBS37 CVBS75 TEST FIELD HSYNC/CB VSYNC XTAL ADDR VAA GND GND DS223PP2 ...
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TQFP Pin Description Pin Name Pin Number V [7: CLKIN 27 ADDR 13 XTAL 12 HSYNC/CB 10 VSYNC 11 FIELD PDAT [7:0] 17,18,19,20,21,22,23,24 SDA 29 SCL 30 ...
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TQFP PACKAGE DRAWING DIM DS223PP2 INCHES MIN MAX 0.000 0.065 0.002 0.006 0.012 0.018 0.478 0.502 0.404 0.412 0.478 0.502 0.404 0.412 0.029 0.037 0.018 0.030 0.000 ...
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