m5lv-128-104-10yi Lattice Semiconductor Corp., m5lv-128-104-10yi Datasheet
m5lv-128-104-10yi
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m5lv-128-104-10yi Summary of contents
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FEATURES High logic densities and I/Os for increased logic integration — 128 to 512 macrocell densities — 256 I/Os Wide selection of density and I/O combinations to support most application needs — 6 macrocell density options — 7 ...
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... CNT Typical Static Power (mA) IEEE 1149.1 Boundary Scan Compliant PCI-Compliant Note: 1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices. GENERAL DESCRIPTION ® The MACH 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1) ...
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... ® block device integration and a wide range M5-256/1 M5-320 M5-192/1 M5LV-256 M5LV-320 68*, 74 68* 68* 68 104 104* 104* 104* 120 120 120 120* 160 160 ...
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IEEE 1149.1 Test Access Port (TAP) interface. FUNCTIONAL DESCRIPTION The MACH 5 architecture consists of PAL blocks connected by two levels of ...
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Block Feeder Product-Term Array and Logic Allocator The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters . A cluster is a sum- ...
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Macrocells The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of ...
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Clock Line 1 Options Global clock ( with positive edge clock enable Global clock ( with negative edge clock enable Global clock ( with positive and negative edge ...
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OE Generator There is one output enable (OE) generator per PAL block that generates two product-term driven output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can choose to be permanently enabled, ...
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MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and ...
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MULTIPLE I/O AND DENSITY OPTIONS The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose a device close to their logic density and I/O requirements, thus minimizing costs. For the same ...
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SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V V MACH 5 devices are safe for mixed supply voltage system designs. CC The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, ...
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V rise must be monotonic and the clock must be inactive until the reset CC delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized ...
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MACH 5 PAL BLOCK Switch Matrix Control Generator ...
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BLOCK DIAGRAM — M5(LV)-128/XXX Block A/Macrocells 0-15 16 I/O Cells 2 Macrocells Macrocells 2 I/O Cells 16 Block B/Macrocells 0-15 CLK0 CLK1 CLK2 4 CLK3 SEGMENT 0 Block D/Macrocells ...
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BLOCK DIAGRAM — M5-192/XXX MACH 5 Family 20446G-008 15 ...
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BLOCK DIAGRAM — M5(LV)-256/XXX 16 MACH 5 Family 20446G-009 ...
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BLOCK DIAGRAM — M5(LV)-320/XXX MACH 5 Family 20446G-010 17 ...
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BLOCK DIAGRAM — M5(LV)-384/XXX 18 MACH 5 Family 20446G-011 ...
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BLOCK DIAGRAM — M5(LV)-512/XXX Continued MACH 5 Family 20446G-012 19 ...
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BLOCK DIAGRAM — M5(LV)-512/XXX 20 Continued MACH 5 Family 20446G-013 ...
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ABSOLUTE MAXIMUM RATINGS M5 Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Device Junction Temperature (Note +130°C or ...
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... ABSOLUTE MAXIMUM RATINGS M5LV Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Device Junction Temperature . . . . . . . . . . . . . +130°C Supply Voltage with Respect to Ground . . . . . . . . . . . -0 +4 Input Voltage . . . . . . . . . . . . . . . . . -0 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (-40°C to +85° 200 mA Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure ...
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: Internal combinatorial propagation t PDi delay t Combinatorial propagation delay PD Registered Delays: t Synchronous clock setup time SS t Asynchronous clock setup time SA t Synchronous clock hold time HS t ...
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Power Delays: t Power level 1 delay (Note 2) PL1 t Power level 2 delay (Note 2) PL2 t Power level 3 delay (Note 2) PL3 Additional Cluster Delay: t Product term cluster delay ...
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Frequency: External feedback, PAL block level. Min of 1/( 1/( WLS WHS SS COS Internal feedback, PAL block level. Min f MAX of 1/( ...
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... M5-192/1 low power M5-128/1 and M5LV-128 low power Frequency (MHz) Curves at High/Low Power Modes CC MACH 5 Family Typ Unit M5(LV)-512 high power M5(LV)-384 high power M5(LV)-320 high power M5-256/1 and M5LV-25 high power M5-192/1 high power M5-128/1 and M5LV-128 high power 20446G-048 ...
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M5-256 low power M5-192 low power 100 M5-128 low power 0 Figure 25º M5-128 high power Frequency (MHz) Curves at High/Low Power Modes ...
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... V = Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-128 M5LV-128* M5-192* M5-256* M5LV-256 80 GND 79 GND 78 TDO 77 I/O51 3A12 2A12 0D14 76 I/O50 3B13 2B13 0C13 75 I/O49 3B12 2B12 0C12 ...
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... Connect 100-Pin TQFP (68 I/ Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-128 M5LV-128 M5-192 M5-256 M5LV-256* 75 GND 74 TDO 73 I/O51 3A12 2A12 0D14 72 I/O50 3B13 2B13 0C13 71 I/O49 3B12 2B12 ...
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... I = Input I/O = Input/Output Connect 30 100-Pin TQFP (74 I/ Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5LV-128 M5LV-256 75 GND 74 TDO 73 I/O54 3A12 0D14 72 I/O53 3B13 0C13 71 I/O52 3B12 0C12 70 I/O51 3B11 0C11 ...
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... PQFP V = Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-128 M5LV-128* M5-192* M5-256* M5LV-256* 108 TDO 107 I/O77 3A8 2A12 0D14 106 I/O76 3A9 2A13 0C13 105 I/O75 3A10 2A14 ...
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... Input/Output Connect 32 144-Pin TQFP V = Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5LV-128 M5LV-256 108 TDO 107 I/O77 3A8 0D14 106 I/O76 3A9 0C13 105 I/O75 3A10 0C12 104 I/O74 ...
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... PQFP (128, 192, 256 Macrocells Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-128 M5LV-128 M5-192 M5-256 M5LV-256 120 TDO 119 I/O91 3A8 2A12 0D14 118 I/O90 3A9 2A13 0D15 117 I/O89 3A10 ...
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... PQFP (320, 384, 512 Macrocells Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512 120 TDO 119 I/O91 5A2 4A2 3A2 118 I/O90 5A3 4A3 3A3 117 I/O89 5A4 4A4 ...
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... I/O88 2B13 115 GND 114 V CC 113 I/O87 2A15 112 I/O86 2A14 111 I/O85 2A13 110 I/O84 2A12 I/O83 109 2A11 108 I/O82 2A10 107 I/O81 2A9 106 I/O80 2A8 105 TMS M5-256 M5LV-256 20446G-023 Macrocell (0-15) PAL Block (A-D) Segment (0-3) 35 ...
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... PQFP (320, 384, 512 Macrocells Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 156 TDO 155 I/O119 5A2 4A2 154 I/O118 5A3 4A3 153 I/O117 5A4 4A4 152 I/O116 ...
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BGA CONNECTION DIAGRAM — M5-320 Bottom View (I/O Pin-outs) 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test Data In ...
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BGA CONNECTION DIAGRAM — M5-320 Bottom View (Macrocell Association) 38 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test Data ...
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... BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out MACH 5 Family 20446G-030 ...
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... BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (Macrocell Association) 40 352-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out Macrocell (0-15) ...
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M5 ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. . FAMILY TYPE M5- = MACH 5 (5 ...
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... M5LV ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. FAMILY TYPE M5LV- = MACH 5 Low Voltage (3.3 MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells ...