LP3942YQ NSC [National Semiconductor], LP3942YQ Datasheet - Page 5

• Manufacturer Part Number: LP3942YQ
• Description: The Dual RGB LED Controller with 1.5x/2x Charge Pump and SPI Interface
• Manufacturer: NSC [National Semiconductor]

LOGIC INPUTS
V
V
I
f
t
H
SPI
NRST
Symbol
IL
IH
Logic Interface Characteristics (1.8V Logic)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
140˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe
Package (LLP).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
dissipation of the device in the application (P
following equation: T
Note 7: Junction-to-ambient thermal resistance (θ
standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W.
The value of θ
power dissipation exists (high V
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: C
C
minimum effective capacitance value is 3.0 µF.
Note 10: Output voltage accuracy does not include V
Note 11: The quiescent current does not include the current setting resistors’ current.
IN
, C
1
, and C
IN
, C
Input Low Level
Input High Level
Logic Input Current
Interface Clock
Reset Pulse Width
JA
2
OUT
capacitors is 70% of nominal value. This tolerance includes manufacturing tolerance, temperature coefficient and voltage dependency (roll-off). C
of the LP3942 in LLP-24 could vary widely, depending on PWB material, layout, and environmental conditions. In applications where high maximum
, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Minimum capacitance value for
A-MAX
= T
Parameter
J-MAX-OP
IN
, high I
− (θ
OUT
JA
A-MAX
D-MAX
), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to
x P
JA
) is dependent on the maximum operating junction temperature (T
D-MAX
), and the junction-to ambient thermal resistance of the part/package in the application (θ
) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
DD
).
(2.78V supply voltage) tolerance.
SS, SI, SCK, NRST
SS, SI, SCK, NRST
SS, SI, SCK
NRST (1 MΩ pull-down)
NRST
Conditions
5
Min
1.2
−1
−1
50
J-MAX-OP
J
= 160˚C (typ.) and disengages at T
Limit
Typ
= 105˚C), the maximum power
Max
JA
0.5
10
1
3
), as given by the
www.national.com
Units
MHz
µA
µA
µs
V
V
OUT
J
=