AD5112 AD [Analog Devices], AD5112 Datasheet - Page 9

• Manufacturer Part Number: AD5112
• Manufacturer: AD [Analog Devices]

Data Sheet
INTERFACE TIMING SPECIFICATIONS
V
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
TIMING DIAGRAMS
CLK
1
2
3
4
5
6
7
8
9
10
EEPROM_PROGRAM
POWER_UP
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
Maximum time after V
DD
R
CLK
U/D
WB
CS
EEPROM
= 2.3 V to 5.5 V; all specifications T
2
CLK
U/D
CS
t
Figure 2. Increment/Decrement Mode Timing
1
1
t
DD
Figure 3. Storage Mode Timing
1
t
is equal to 2.3 V.
2
Test Conditions/Comments
V
V
V
V
V
V
V
V
V
V
t
DATA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
4
t
≥ 2.7 V
< 2.7 V
≥ 2.7 V
< 2.7 V
≥ 2.7 V
< 2.7 V
≥ 2.7 V
< 2.7 V
≥ 2.7 V
< 2.7 V
8
t
3
t
6
t
5
t
6
MIN
to T
NEW DATA
t
EEPROM_PROGRAM
t
7
MAX
t
10
, unless otherwise noted.
25
10
20
10
20
15
6
20
40
15
12
24
12
1
Min
Rev. 0 | Page 9 of 24
Typ
15
Max
50
25
50
50
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
CLK
U/D
CS
Description
Clock frequency
CS setup time
CLK low time
CLK high time
U/D setup time
U/D hold time
CS rise to CLK hold time
CS rising edge to next CLK ignored
U/D minimum pulse time
U/D rise to CLK falling edge
Minimum CS time
Memory program time
Power-on EEPROM restore time
Figure 4. Shutdown Mode Timing
t
1
AD5111/AD5113/AD5115
t
9
t
6