ASM2I99456G-32-ER PULSECORE [PulseCore Semiconductor], ASM2I99456G-32-ER Datasheet - Page 5

• Manufacturer Part Number: ASM2I99456G-32-ER
• Description: 3.3V/2.5V LVCMOS Clock Fanout Buffer
• Manufacturer: PULSECORE [PulseCore Semiconductor]

November 2006
rev 0.3
Table 7. AC Characteristics
Note: 1 AC characteristics apply for parallel output termination of 50Ω  t o V
Table 8. DC Characteristics
Symbol
Note:1 V
Symbol
V
I
Z
t
V
t
V
V
CCQ
V
t
V
V
CMR
PLZ
t
PZL
I
P
t
OUT
t
DC
f
sk(PP)
V
t
t
IN
t
SK(P)
t
PP
OH
OL
sk(O)
2 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
3 Input pull-up / pull-down resistors influence input current.
4 I
MAX
CMR
,
IH
f
PLH
PHL
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
IL
r
r
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 V
5 Output pulse skew is the absolute difference of the propagation delay times: | t
ref
, t
, t
PP
swing lies within the V
REF
,
,
4
transmission line to a termination voltage of V
CCQ
1
CMR
Q
swing lies within the V
f
f
output duty cycle and maximum frequency specifications.
HZ
LZ
CMR
3
is the DC current consumption of the device with all outputs open and the input in its default state or open
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input high voltage
Input low voltage
Peak-to-peak Input voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output impedance
Input current
Maximum Quiescent Supply Current
Input Frequency
Maximum Output
Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Output-to-output
Skew
Device-to-device Skew
Output pulse skew
Output Duty Cycle
Output Rise/Fall Time
Characteristics
PP
PP
3
(DC) specification.
(AC) specification.
Characteristics
5
(VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, T
(VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T
Notice: The information in this document is subject to change without notice.
Any output bank, same output
Any output, Any output divider
3.3V/2.5V LVCMOS Clock Fanout Buffer
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
PCLK
PCLK
Within one bank
CCLK to any Q
CCLK to any Q
÷1 output
÷2 output
÷1 output
÷2 output
Min
TT
divider
-0.3
250
1.7
1.1
1.8
PCLK
PCLK
.
PLH
Min
500
1.3
1.4
2.2
2.2
0.1
17 - 20
47
45
0
0
0
- t
A
A
Typ
PHL
= -40 to +85°C)
= -40 to +85°C)
|.
2
Typ
2.8
2.8
50
50
V
V
CC
1
Max
±200
CC
0.7
0.6
2.0
+ 0.3
-0.7
VCC-
Max
1000
250
250
4.45
2.25
1.0
125
150
200
350
200
0.8
4.2
1.0
10
10
53
55
4
2
2
Unit
mV
mA
µA
V
V
V
V
V
Ω
Unit
MHz
MHz
MHz
mV
nS
nS
nS
nS
nS
nS
pS
pS
pS
nS
pS
nS
%
%
V
ASM2I99456
LVCMOS
LVCMOS
LVPECL
LVPECL
I
I
V
All VCC Pins
OH
OL
CMR
IN
DC
CMR
= 15 mA
=-24 mA
=GND or V
range and the input
DC
Condition
range and the input
REF
0.55 to 2.4V
Condition
0.8 to 2.0V
FSELx=0
FSELx=1
LVPECL
LVPECL
REF
= 25%-75%
5 of 14
= 50%
2
IN
=V
CC