MG84FL54BD MEGAWIN [Megawin Technology Co., Ltd], MG84FL54BD Datasheet - Page 48

• Manufacturer Part Number: MG84FL54BD
• Description: Full-Speed USB micro-controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

16.2.3. Mode Change on /SS-pin
If SPEN=1, SSIG=0, MSTR=1 and /SS pin=1, the SPI is enabled in master mode. In this case, another master
can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus contention,
the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be
an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an
SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a slave select
and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it
will stay in slave mode.
16.2.4. No Write Collision
The SPI is Dual Buffered in the transmit direction and also Dual Buffered in the receive direction. New data for
transmission can not be written to the Transmit Holding Register (THR) until the previous data is loaded to the
Output Shift Register to be transmitted. The THRE (SPSTAT.6) bit is set to indicate the user can write a new
data byte to the THR for the following proceeding transmission. This architecture makes higher throughput
compared to the one with Write Collision indication.
16.2.5. SPI Clock Rate Select
The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCTL register, as shown
below.
Table: Serial Clock Rates
Where, Fosc is the system clock.
48
SPR2
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SPI Clock Rate @ Fosc=12MHz
MG84FL54B Data Sheet
750 KHz
500 KHz
250 KHz
125 KHz
1.5 MHz
3 MHz
2 MHz
1 MHz
Fosc divided by
12
16
24
48
96
4
6
8
MEGAWIN