AD5282 Analog Devices, AD5282 Datasheet - Page 3

• Manufacturer Part Number: AD5282
• Description: +15V/ I2C Compatible Digital Potentiometers
• Manufacturer: Analog Devices

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
V
Parameter
DYNAMIC CHARACTERISTICS
Bandwidth –3dB
Total Harmonic Distortion
V
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
NOTES:
1.
2.
3.
4.
5.
6.
9.
10.
11.
12.
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
W
A
Fall Time of both SDA & SCL signals
Rise Time of both SDA & SCL signals
= +V
Settling Time
Bus free time between
Low Period of SCL Clock
Typicals represent average readings at +25°C, V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
result in the minimum overall power consumption.
P DISS is calculated from (I DD x V DD ). CMOS logic level inputs result in minimum power dissipation.
All dynamic characteristics use V
See timing diagram for location of measured values.
High Period of SCL Clock
AB
Hold Time (repeated START)
Setup Time For START Condition t5
Data Hold Time
Data Setup Time
Setup time for STOP Condition
DD
= V
, V
DD
, Wiper (V
B
= 0V, -40°C < T
W
) = No connect
STOP & START
PRELIMINARY TECHNICAL DATA
W
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
6,9,11
= +5V.
A
< +85°C unless otherwise noted.)
Symbol
BW_20K
BW_50K
BW_200K
THD
t
e
DD
S
N_WB
f
t10
t1
t2
t3
t4
t6
t7
t8
t9
SCL
= +5V, V
W
SS
= -5V.
R
R
V
V
R
After this period the first clock pulse is generated
Conditions
R
AB
AB
AB
A
A
WB
= V
=1Vrms + 2V dc, V
= 20K , Code = 80
= 50K , Code = 80
= 200K , Code = 80
= 10K , f = 1KHz
DD
, V
B
=0V, ±1 LSB error band
3
B
H
H
= 2V DC, f=1KHz
H
A
= V
Min
100
1.3
0.6
1.3
0.6
0.6
0.6
DD
0
0
and V
AD5280/AD5282
(V
B
DD
= 0V.
Typ
0.005
650
142
= +5V, V
69
14
2
1
SS
Max
400
300
300
0.9
= -5V, V
LOGIC
nV Hz
Units
= +5V,
KHz
kHz
kHz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
%