AD7870 Analog Devices, AD7870 Datasheet - Page 6

• Manufacturer Part Number: AD7870
• Description: LC2MOS Complete/ 12-Bit/ 100 kHz/ Sampling ADCs
• Manufacturer: Analog Devices

PIN FUNCTION DESCRIPTION
DIP
Pin No.
1
2
3
4
5
6
7
8–11
12
13–16
17
18
19
20
21
22
23
24
AD7870/AD7875/AD7876
Pin
Mnemonic
RD
BUSY/INT
CLK
DB11/HBEN
DB10/SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an
DB9/SCLK
DB8/SDATA
DB7/LOW–
DB4/LOW
DGND
DB3/DB11–
DB0/DB8
V
AGND
REF OUT
V
V
12/8/CLK
CONVST
CS
HBEN
HIGH
LOW
DD
IN
SS
DB7/LOW DB6/LOW
LOW
DB7
DIP and SOIC
Function
Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
Busy/Interrupt, Active low logic output indicating converter status. See timing diagrams.
Clock input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this pin to
V
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/8/CLK input (see
below). When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin
becomes the HBEN logic input HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DB0/DB8
become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see Table I).
active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 k pull-up
resistor is required on SSTRB.
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated
serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at –5 V, then SCLK
runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an
open-drain output and requires an external 2 k pull-up resistor.
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is an open-
drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data is valid on the fall-
ing edge of SCLK while SSTRB is low. An external 4.7 k pull-up resistor is required on SDATA.
Three-state data outputs controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN inputs.
With 12/8/CLK high, they are always DB7–DB4. With 12/8/CLK low or –5 V, their function is controlled by HBEN
(see Table I).
Digital Ground. Ground reference for digital circuitry.
Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN
inputs. With 12/8/CLK high, they are always DB3–DB0. With 12/8/CLK low or –5 V, their function is controlled by
HBEN (see Table I).
Positive Supply, +5 V
Analog Ground. Ground reference for track/hold, reference and DAC.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 A.
Analog Input. The analog input range is 3 V for the AD7870, 10 V for the AD7876 and 0 V to +5 V for the AD7875.
Negative Supply, –5 V
Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for-
mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous.
With this pin at –5 V, either byte or serial data is again available but SCLK is now continuous.
Convert Start. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.
This input is asynchronous to the CLK input.
Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new
conversion is initiated when CS goes low.
SS
enables the internal laser-trimmed clock oscillator.
LOW
DB6
2
DB5/LOW DB4/LOW DB3/DB11
LOW
DB5
Table I. Output Data for Byte Interfacing
5%.
5%.
1
2
PIN CONFIGURATIONS ARE THE SAME FOR
THE AD7870 AND AD7875 ARE AVAILABLE IN
THE AD7875 AND AD7876.
DIP AND PLCC; THE AD7870A IS AVAILABLE IN
PLASTIC DIP; THE AD7875 AND AD7876 ARE
AVAILABLE IN SOIC AND DIP.
PIN CONFIGURATIONS
LOW
DB4
–6–
DB11(MSB)
DB3
1
DB2/DB10
DB10
DB2
DB1/DB9 DB0/DB8
DB9
DB1
PLCC
2
DB0 (LSB)
DB8
REV. B