IDT23S09-1PG Integrated Device, IDT23S09-1PG Datasheet

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IDT23S09-1PG

Manufacturer Part Number
IDT23S09-1PG
Description
IDT23S09 3.3V ZERO DELAY CLOCK BUFFER / SPREAD SPECTRUM COMPATIBLE
Manufacturer
Integrated Device
Datasheet
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT23S09-1 for Standard Drive
• IDT23S09-1H for High Drive
• No external RC network required
• Operates at 3.3V V
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
c
four outputs
2003 Integrated Device Technology, Inc.
DD
REF
S2
S1
9
1
8
3.3V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
PLL
Control
Logic
1
DESCRIPTION:
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT23S09 enters power down. In this mode, the device will draw less than
12µA for Commercial Temperature range and less than 25µA for Industrial
temperature range, and the outputs are tri-stated.
operation.
The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,
The IDT23S09 is characterized for both Industrial and Commercial
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
16
10
2
11
3
14
15
6
7
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
OCTOBER 2003
IDT23S09
DSC - 6395/3

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IDT23S09-1PG Summary of contents

Page 1

... REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S09 enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated ...

Page 2

... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION REF 1 2 CLKA1 CLKA2 GND 6 CLKB1 CLKB2 SOIC/ TSSOP TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number ...

Page 3

... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured (2) DD Measured PLL bypass mode (IDT23S09 only) (2) DD Measured the CLKOUT pins of devices DD Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...

Page 4

... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT23S09 only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...

Page 5

... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT23S09 only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...

Page 6

... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay ...

Page 7

... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER TEST CIRCUITS V DD 0.1µF OUTPUTS V DD 0.1µF GND GND Test Circuit 1 (all Parameters Except t8) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CLK OUT 0.1µF C LOAD 0.1µF Test Circuit 2 (t8, Output Slew Rate On -1H Devices 1KΩ OUTPUTS 1KΩ ...

Page 8

... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER ORDERING INFORMATION IDT XXXXX XX Device Type Package Process Ordering Code IDT23S09-1DC IDT23S09-1DCI IDT23S09-1HDC IDT23S09-1HDCI IDT23S09-1HPG IDT23S09-1HPGI CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES X Blank 23S09-1 23S09-1H Package Type 16-Pin SOIC ...

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