LTC6252 Linear Technology, LTC6252 Datasheet - Page 7

• Manufacturer Part Number: LTC6252
• Description: 3.5mA Power Efficient Rail-to-Rail I/O Op Amps
• Manufacturer: Linear Technology

DataSheet.in
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes. If any of
the input or shutdown pins goes 300mV beyond either supply or the
differential input voltage exceeds 1.4V the input current should be limited
to less than 10mA. This parameter is guaranteed to meet specifi ed
performance through design and/or characterization. It is not production
tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output current is high. This
parameter is guaranteed to meet specifi ed performance through design
and/or characterization. It is not production tested.
Note 4: The LTC6252C/LTC6253C/LTC6254C and LTC6252I/LTC6253I/
LTC6254I are guaranteed functional over the temperature range of –40°C
to 85°C. The LTC6252H/LTC6253H/LTC6254H are guaranteed functional
over the temperature range of –40°C to 125°C.
Note 5: The LTC6252C/LTC6253C/LTC6254C are guaranteed to meet
specifi ed performance from 0°C to 70°C. The LTC6252C/LTC6253C/
LTC6254C are designed, characterized and expected to meet specifi ed
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. The LTC6252I/LTC6253I/LTC6254I are guaranteed
to meet specifi ed performance from –40°C to 85°C. The LTC6252H/
LTC6253H/LTC6254H are guaranteed to meet specifi ed performance from
–40°C to 125°C.
TYPICAL PERFORMANCE CHARACTERISTICS
40
35
30
25
20
15
10
5
0
–250
V
(MS, PNP Stage)
V
V
OS
S
CM
= 5V, 0V
= 2.5V
Distribution, V
–150
INPUT OFFSET VOLTAGE (μV)
–50
CM
50
= V
S
150
/2
625234 G01
250
40
35
30
25
20
15
10
5
0
–250
V
(TSOT-23, PNP Stage)
V
V
OS
S
CM
= 5V, 0V
= 2.5V
Distribution, V
–150
INPUT OFFSET VOLTAGE (μV)
–50
Note 6: Supply voltage range is guaranteed by power supply rejection ratio
test.
Note 7: The input bias current is the average of the average of the currents
at the positive and negative input pins.
Note 8: Matching parameters are the difference between amplifi ers A and
D and between B and C on the LTC6254; between the two amplifi ers on the
LTC6253.
Note 9: Thermal resistance varies with the amount of PC board metal
connected to the package. The specifi ed values are with short traces
connected to the leads with minimal metal area.
Note 10: The output voltage is varied from 0.5V to 4.5V during
measurement.
Note 11: Middle 2/3 of the output waveform is observed. R
supply.
Note 12: The output voltage is varied from 0.5V to 2.2V during
measurement.
Note 13: FPBW is determined from distortion performance in a gain of +2
confi guration with HD2, HD3 < –40dBc as the criteria for a valid output.
Note 14: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set.
LTC6252/LTC6253/LTC6254
CM
50
= V
S
150
/2
625234 G02
250
16
14
12
10
–2000
8
6
4
2
0
V
(MS, NPN Stage)
V
V
OS
S
CM
= 5V, 0V
Distribution, V
= 4.5V
–1200
INPUT OFFSET VOLTAGE (μV)
–400
CM
400
L
= V
= 1k to half
+
1200
– 0.5V
625234 G03
625234f
7
2000