MAX1192 Maxim, MAX1192 Datasheet - Page 26

• Manufacturer Part Number: MAX1192
• Description: Ultra-Low-Power / 22Msps / Dual 8-Bit ADC
• Manufacturer: Maxim

THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V
the amplitudes of the 2nd- through 6th-order harmonics.
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 ±f2), (2 x f1), (2 x f2), (2 x f1 ±f2), (2 x f2
±f1). The individual input tone levels are at -7dB FS.
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
26
THD
______________________________________________________________________________________
Spurious-Free Dynamic Range (SFDR)
=
1
20
is the fundamental amplitude, and V
×
Intermodulation Distortion (IMD)
Total Harmonic Distortion (THD)
Third Harmonic Distortion (HD3)
log





V
2
2
+
V
3
2
+
V
V
1
4
2
+
V
5
2
2
+
–V
V
6
6
2
are





IM3 is the power of the worst third-order intermodula-
tion product relative to the input power of either input
tone when two tones, f1 and f2, are present at the
inputs. The third-order intermodulation products are (2
x f1 ±f2), (2 x f2 ±f1). The individual input tone levels
are at -7dB FS.
Power-supply rejection is defined as the shift in offset
and gain error when the power supplies are moved ±5%.
A small -20dB FS analog input signal is applied to an
ADC in such a way that the signal’s slew rate will not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
TRANSISTOR COUNT: 7925
PROCESS: CMOS
Third-Order Intermodulation (IM3)
Power-Supply Rejection
Small-Signal Bandwidth
Full-Power Bandwidth
Chip Information