ADC12L030CIWM National Semiconductor, ADC12L030CIWM Datasheet - Page 9

• Manufacturer Part Number: ADC12L030CIWM
• Description: 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
• Manufacturer: National Semiconductor

t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
Symbol
SPU
ACC
SET-UP
DELAY
1H
HDI
SDI
HDO
DDO
RDO
FDO
CD
SD
The following specifications apply for V
sion mode, t
with fixed 1.250V common-mode voltage, and 10(t
= T
IN
OUT
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
T
, t
J
max = 150˚C. The typical thermal resistance (
J
0H
= T
MIN
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge
Access Time Delay from
CS Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
Delay from SCLK Falling
Edge to CS Falling Edge
Delay from CS Rising Edge to
DO TRI-STATE
DI Hold Time from Serial Data
Clock Rising Edge
DI Set-Up Time from Serial Data
Clock Rising Edge
DO Hold Time from Serial Data
Clock Falling Edge
Delay from Serial Data Clock
Falling Edge to DO Data Valid
DO Rise Time, TRI-STATE to High
DO Rise Time, Low to High
DO Fall Time, TRI-STATE to Low
DO Fall Time, High to Low
Delay from CS Falling Edge
to DOR Falling Edge
Delay from Serial Data Clock Falling
Edge to DOR Rising Edge
Capacitance of Logic Inputs
Capacitance of Logic Outputs
r
to T
= t
f
MAX
= 3 ns, f
; all other limits T
Parameter
CK
IN
) at any pin exceeds the power supplies (V
= f
SK
= 5 MHz, R
A
+
JA
D
= T
= V
) of these parts when board mounted follow:
= (T
J
A
J
+ = V
= 25˚C. (Note 17)
max − T
S
= 25 , source impedance for V
(Continued)
CK
D
A
+ = +3.3 V
) acquisition time unless otherwise specified. Boldface limits apply for T
)/
R
R
R
R
L
L
L
L
JA
= 3k, C
= 3k, C
= 3k, C
= 3k, C
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
Conditions
IN
DC
9
L
L
L
L
<
, V
= 100 pF
= 100 pF
= 100 pF
= 100 pF
GND or V
REF
+ = +2.500 V
IN
>
V
A
+ or V
REF
J
max,
+ and V
D
DC
(Note 10)
+), the current at that pin should be limited to 20 mA.
Typical
JA
, V
500
25
70
35
50
10
10
15
15
50
45
10
20
and the ambient temperature, T
0
5
5
REF
REF
− = 0 V
−
25 , fully-differential input
(Note 11)
DC
Limits
700
100
, 12-bit + sign conver-
60
50
15
10
65
90
40
40
40
40
80
80
5
5
A
. The maximum
www.national.com
µs (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
(Limits)
Units
pF
pF
A