LM85 National Semiconductor, LM85 Datasheet - Page 11

• Manufacturer Part Number: LM85
• Description: Hardware Monitor with Integrated Fan Control
• Manufacturer: National Semiconductor

Register
Address
30h
31h
32h
Register
Address
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Functional Description
4.3 Register 28-2Fh: Fan Tachometer Reading
The Fan Tachometer Reading registers contain the number of 11.111 µs periods (90 kHz) between full fan revolutions. The results
are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full revolution. These
registers will be updated at least once every second.
The value, for each fan, is represented by a 16-bit unsigned number.
The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled
or non-functional.
The least two significant bits (LEVEL1 and LEVEL2) of the least significant byte are used to indicate the accuracy level of the
tachometer reading. The accuracy ranges from most to least accurate. [LEVEL1:LEVEL2]=11indicates a most accurate value,
[LEVEL1:LEVEL2]=01 indicates the least accurate value and [LEVEL1:LEVEL2]=00 is reserved for future use.
FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. These registers are
read only — a write to these registers has no effect.
When the least significant byte (LSByte) of the LM85C 16-bit register is read, the other byte (MSByte) is latched at the current
value until it is read. This is required to ensure a valid reading. The LM85C will update the Fan Tachometer Reading registers at
the start of an LSByte read. Therefore, reading the MSByte register twice in a row will yield the same data.
When the LSByte of the LM85B 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At
the end of the MSByte read the Fan Tachometer Reading registers are updated.
During spin-up, the PWM duty cycle reported is 0%.
4.4 Register 30-32h: Current PWM Duty
The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle is
100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this register
and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section.
When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read only unless the fan is
in manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan. The PWM
duty cycle is represented as shown in the following table.
Read/
Write
R/W
R/W
R/W
Read/
Write
R
R
R
R
R
R
R
R
Register
Name
Fan1 Current PWM Duty
Fan2 Current PWM Duty
Fan3 Current PWM Duty
Register
Name
Tach1 LSB
Tach1 MSB
Tach2 LSB
Tach2 MSB
Tach3 LSB
Tach3 MSB
Tach4 LSB
Tach4 MSB
TABLE 1. Temperature vs Register Reading (Continued)
(SENSOR ERROR)
Current Duty
Temperature
Bit 7
(MSB)
7
15
7
15
7
15
7
15
0.3922%
25.098%
(Continued)
0%
.
.
.
Bit 6
6
14
6
14
6
14
6
14
Bit 7
(MSB)
7
7
7
Value (Decimal)
Bit 5
5
13
5
13
5
13
5
13
Reading (Dec)
Bit 6
6
6
6
11
64
0
1
.
.
.
Bit 4
4
12
4
12
4
12
4
12
Bit 5
5
5
5
Bit 3
3
11
3
11
3
11
3
11
Bit 4
4
4
4
Value (Hex)
Reading (Hex)
00h
01h
40h
.
.
.
80h
Bit 3
3
3
3
Bit 2
2
10
2
10
2
10
2
10
Bit 2
2
2
2
Bit 1
LEVEL1
9
LEVEL1
9
LEVEL1
9
LEVEL1
9
Bit 1
1
1
1
Bit 0
(LSB)
LEVEL0
8
LEVEL0
8
LEVEL0
8
LEVEL0
8
Bit 0
(LSB)
0
0
0
www.national.com
Default
Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Default
Value
N/A
N/A
N/A