XCR3064XL-6CP56I Xilinx, XCR3064XL-6CP56I Datasheet
XCR3064XL-6CP56I
Related parts for XCR3064XL-6CP56I
XCR3064XL-6CP56I Summary of contents
Page 1
... XCR3064XL 64 Macrocell CPLD Product Specification 0 14 Description The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. ...
Page 2
... XCR3064XL 64 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage for 3.3V outputs OL I Input leakage current IL I I/O High-Z leakage current IH I Standby current CCSB (3,4) I Dynamic current CC (5) C Input pin capacitance IN C Clock input capacitance ...
Page 3
... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS017 (v1.6) January 8, 2002 Product Specification -6 Min. Max. - 5.5 (3) - 6.0 - 4.0 2.5 - 3 2 145 - 7.5 (6) - 7.5 - 6.5 - 8.0 ) for recommended operating conditions. www.xilinx.com 1-800-255-7778 XCR3064XL 64 Macrocell CPLD (1,2) -7 -10 Min. Max. Min. Max. - 7.0 - 9.1 - 7.5 - 10.0 - 5.0 - 6.5 2.5 - 3.0 - 4.3 - 5.4 - 4 3.0 - 4.0 - 5 ...
Page 4
... XCR3064XL 64 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast Input buffer delay FIN T Global Clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay LDI ...
Page 5
... V Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified DS017_04_042800 PD2 www.xilinx.com 1-800-255-7778 XCR3064XL 64 Macrocell CPLD Values 390 390 Open Closed Closed Open Closed Closed , pF. Delay measured at + 300 mV, V – ...
Page 6
... XCR3064XL 64 Macrocell CPLD Pin Descriptions Table 2: XCR3064XL User I/O Pins PC44 VQ44 CS48 Total User I/O Pins Table 3: XCR3064XL I/O Pins Function Macro- Block cell PC44 VQ44 CS48 CP56 VQ100 (1) ( ...
Page 7
... R Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No connect Pins Pin Type PC44 IN0 / CLK0 2 IN1 / CLK1 1 IN2 / CLK2 44 IN3 / CLK3 43 TCK 32 TDI 7 TDO 38 TMS 13 (1) PORT_EN 15, 23 GND 22, 30 Connects - Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet ...
Page 8
... VQ100 100-pin Very Thin Quad Flat Package Component Availability Pins Type Plastic VQFP Code XCR3064XL -6 -7, -10 8 XCR3064XL - Package 44-pin Plastic Leaded Chip Carrier 44-pin Very Thin Quad Flat Pack 48-ball Chip Scale Package 56-ball Chip Scale Package 100 56 Plastic BGA Plastic BGA ...
Page 9
... OR array. Updated T SU SU2 spec to match software timing. Added T delay measurement. Updated note Characteristics POD www.xilinx.com 1-800-255-7778 XCR3064XL 64 Macrocell CPLD Revision Table 4 to read: "port enable pin is Table 2: Total User I/O; changed V to page 1. Added single p-term setup time (T spec. Updated T spec ...