SAA7183 Philips Semiconductors, SAA7183 Datasheet
SAA7183
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SAA7183 Summary of contents
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... DATA SHEET SAA7182; SAA7183 Digital Video Encoder (EURO-DENC) Preliminary specification Supersedes data of 1995 Sep 19 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1996 Jul 08 ...
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... Internal Colour Bar Generator (CBG) Overlay with Look-Up Tables (LUTs) 8 Macrovision Pay-per-View protection system as option, also used for RGB output This applies to SAA7183 only. The device is protected by USA patent numbers 461603, 4577216 and 4819098 and other intellectual property rights. QUICK REFERENCE DATA ...
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... C-bus 8 internal control control bus SAA7182 SAA7183 Y CbCr 2, 23, 40, 43, 46, 56, 59 62, 65 Fig.1 Block diagram. 3 Preliminary specification SAA7182; SAA7183 TTXRQ XTALO LLC Y/C/CVBS V DDA4 CREF XTALI V refH2 to V DDA7 75 68 64, 70, 72, 74 SYNC CLOCK 2 I C-bus 8 control ...
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... Raster Control 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse. RTCI 37 Real Time Control Input. If the LLC clock is provided by an SAA7111 or SAA7151B , RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality. 1996 Jul 08 SAA7182; SAA7183 DESCRIPTION 4 Preliminary specification ...
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... Analog supply voltage 5 for the Y/C/CVBS DACs. DDA5 Y 71 Analog output of the luminance signal Analog supply voltage 6 for the Y/C/CVBS DACs. DDA6 CVBS 73 Analog output of the CVBS signal. 1996 Jul 08 SAA7182; SAA7183 DESCRIPTION SSA 5 Preliminary specification . SSA. . DDA . DDA ...
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... Test pin. Connected to digital ground for normal operation digital ground 8 SSD8 V 80 digital supply voltage 8 DDD8 V 81 digital ground 9 SSD9 V 82 digital supply voltage 9 DDD9 2 SCL 83 I C-bus serial clock input. 2 SDA 84 I C-bus serial data input/output. 1996 Jul 08 SAA7182; SAA7183 DESCRIPTION 6 Preliminary specification . SSA ...
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... V SSD3 24 MP7 25 MP6 26 MP5 27 MP4 28 V DDD4 29 V SSD4 30 MP3 31 MP2 32 1996 Jul 08 SAA7182 SAA7183 Fig.2 Pin configuration. 7 Preliminary specification SAA7182; SAA7183 74 V DDA7 73 CVBS 72 V DDA6 DDA5 69 CHROMA 68 I Y/C/CVBS 67 V SSA 66 n. DDA4 63 I RGB 62 n ...
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... The encoder is always timing master for the MPEG port (MP), but it can additionally be configured as slave with respect to the RCV trigger inputs. 1996 Jul 08 SAA7182; SAA7183 European teletext encoding is supported if an appropriate teletext bitstream is applied to the TTX pin. The IC also contains Closed Caption and Extended Data Services Encoding (Line 21), and supports anti-taping signal generation in accordance with Macrovision ...
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... The internal insertion window for text is set to 360 teletext bits including clock run-in bits. For protocol and timing see Fig.17. 1996 Jul 08 SAA7182; SAA7183 C LOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21) ...
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... For RGB outputs fixed amplification in accordance with “CCIR 601” is provided. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. 10 Preliminary specification SAA7182; SAA7183 C-bus interface is a standard slave transceiver, C-bus slave addresses are selected: ...
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... Preliminary specification SAA7182; SAA7183 (1) (2) ( 235 235 235 235 16 235 16 235 235 16 235 ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) 1996 Jul 08 SAA7182; SAA7183 12 Preliminary specification ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) 1996 Jul 08 SAA7182; SAA7183 13 Preliminary specification ...
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... OVL keying disabled for Y, C and CVBS outputs. Data from input ports are encoded. Default after reset. Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7. 14 Preliminary specification SAA7182; SAA7183 ACK -------- DATA n DESCRIPTION DESCRIPTION ...
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... VALUE 68H 92H 82H A4H 15 Preliminary specification SAA7182; SAA7183 INDEX (note 2) OVLV 0 (00H) 0 (00H) 18 (12H) 14 (0EH) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) 112 (70H) 84 (54H) ...
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... IRE BLCKL = 0 BLCKL = 63 (3FH) 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. 16 Preliminary specification SAA7182; SAA7183 REMARKS output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal REMARKS ...
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... DACs for CVBS, Y and C forced to lowest output voltage DACs for R, G and B in normal operational mode; default after reset DACs for R, G and B forced to lowest output voltage 17 Preliminary specification SAA7182; SAA7183 REMARKS (1) output blanking level = 17 IRE output blanking level = 42 IRE ...
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... FSC round = ------- - f see note 1 = 1716 FSC = 569408543 (21F07C1FH). = 1728 FSC = 705268427 (2A098ACBH). llc = 1728 FSC = 681786290 (28A33BB2H). llc 18 Preliminary specification SAA7182; SAA7183 DESCRIPTION REMARKS (1) nominal (2) nominal (3) nominal (4) nominal REMARKS FSC3 = most significant byte 32 2 FSC0 = least significant byte ...
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... RCV1 is switched to input; default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port; default after reset horizontal synchronization is taken from RCV2 port defines signal type on pin RCV1; see Table 21 19 Preliminary specification SAA7182; SAA7183 DESCRIPTION ...
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... SECAM-specific if bit SECAM = 1 reset every eight fields reset every four fields 20 Preliminary specification SAA7182; SAA7183 FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = SECAM = 0), eighth field (PAL = 1) or twelfth fi ...
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... M-systems line = (SCCLN + 1) for other systems Line 21 encoding off enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields DESCRIPTION 21 Preliminary specification SAA7182; SAA7183 FUNCTION DESCRIPTION FUNCTION ...
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... LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse S UBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. 1996 Jul 08 SAA7182; SAA7183 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 22 Preliminary specification ...
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... It is set immediately after the data has been encoded. Not first field of a sequence. During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields, SECAM = 12 fields. During odd field. During even field. 23 Preliminary specification SAA7182; SAA7183 DATA BYTE CCRDO CCRDE 0 DESCRIPTION ...
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... SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 1996 Jul 08 ( Fig.3 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 Fig.4 Chrominance transfer characteristic 2. 24 Preliminary specification SAA7182; SAA7183 MBE735 1.2 f (MHz) 1.6 MBE737 14 f (MHz) ...
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... Fig.5 Total luminance of Y and CVBS; luminance transfer characteristic 1. handbook, halfpage Fig.6 Detailed luminance of Y and CVBS; luminance transfer characteristic 2. 1996 Jul (dB Preliminary specification SAA7182; SAA7183 MBE736 6 f (MHz) MGB707 14 f (MHz) ...
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... G v (dB 1996 Jul Fig.7 Luminance transfer characteristic in RGB Fig.8 Colour difference transfer characteristic in RGB. 26 Preliminary specification SAA7182; SAA7183 MGB708 14 f (MHz) MGB706 14 f (MHz) ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) handbook, full pagewidth (dB 0.2 handbook, full pagewidth 30 (deg 0.2 1996 Jul 08 0.4 0.6 0.8 Fig.9 Gain of SECAM pre-emphasis. 0.4 0.6 0.8 Fig.10 Phase of SECAM pre-emphasis. 27 Preliminary specification SAA7182; SAA7183 1 1.2 1.4 f (MHz) 1 1.2 1.4 f (MHz) MGB705 1.6 MGB704 1.6 ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) handbook, full pagewidth (dB 0.2 handbook, full pagewidth 80 (deg 0.2 1996 Jul 08 0.4 0.6 0.8 Fig.11 Gain of SECAM anti-Cloche. 0.4 0.6 0.8 Fig.12 Phase of SECAM anti-Cloche. 28 Preliminary specification SAA7182; SAA7183 1 1.2 1.4 f (MHz) 1 1.2 1.4 f (MHz) MGB703 1.6 MGB702 1.6 ...
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... CDIR, SCL, SDA, RESET, AP and SP) 1996 Jul 08 note 1 note 1 clocks data I/Os at high impedance note 2 note 2 note LOW or HIGH during acknowledge note 3 note 4 LLC note 3 note 3 29 Preliminary specification SAA7182; SAA7183 CONDITIONS MIN. 4.75 4.75 0.5 2.0 2.4 0 2.4 2.6 0.5 3 MAX. UNIT 5.25 V 5.25 ...
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... For full digital range, without load, V voltage (digital zero at DAC) is 0.2 V. 1996 Jul 08 CONDITIONS 3rd harmonic note 5 note 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output DDA 30 Preliminary specification SAA7182; SAA7183 MIN. MAX. UNIT 30 MHz ...
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... HIGH t HD; DAT LLC t HIGH t HD; DAT t f valid not valid HD; DAT valid not valid Fig.13 Clock data timing. Cb(0) Y(0) Fig.14 Functional timing. 31 Preliminary specification SAA7182; SAA7183 valid valid MBE742 Cr(0) Y(1) 2.6 V 1.5 V 0.6 V 2.4 V 1.5 V 0.8 V 2.0 V 0.8 V 2.4 V 0.6 V Cb(2) MGB699 ...
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... SAA7111 provides ( bits, resulting in 3 reserved bits before sequence bit. 1996 Jul 08 Y(0) Y(1) Cb(0) Cr(0) Fig.15 Digital TV timing. 4 bits reserved HPLL increment not used in SAA7182/83 Y) line inverted. Fig.16 RTCI timing. 32 Preliminary specification SAA7182; SAA7183 Y(2) Y(3) Cb(2) Cr(2) sequence 5 bits reserved FSCPLL increment (4) valid invalid 8/LLC sample sample Y(4) Cb(4) MBE739 reserved (2) bit (1) reset bit (1) ...
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... TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion Fig.17 Teletext timing diagram. 33 Preliminary specification SAA7182; SAA7183 t TTXWin 1/LLC 1/LLC 24 MGB701 ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) APPLICATION INFORMATION 1996 Jul 08 SAA7182; SAA7183 34 Preliminary specification ...
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... 0.81 29.41 29.41 28.70 28.70 30.35 1.27 0.66 29.21 29.21 27.69 27.69 30.10 0.032 1.158 1.158 1.130 1.130 1.195 0.05 0.026 1.150 1.150 1.090 1.090 1.185 REFERENCES JEDEC EIAJ 35 Preliminary specification SAA7182; SAA7183 detail max. 30.35 1.22 1.44 0.51 0.18 0.18 30.10 1.07 1.02 1.195 ...
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... This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Jul 08 SAA7182; SAA7183 If wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jul components conveys a license under the Philips’ system provided the system conforms to the I 37 Preliminary specification SAA7182; SAA7183 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) 1996 Jul 08 SAA7182; SAA7183 NOTES 38 Preliminary specification ...
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... Philips Semiconductors Digital Video Encoder (EURO-DENC) 1996 Jul 08 SAA7182; SAA7183 NOTES 39 Preliminary specification ...
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... Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. + 24825 © Philips Electronics N.V. 1996 All rights are reserved ...