SAA7188 Philips Semiconductors, SAA7188 Datasheet
SAA7188
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SAA7188 Summary of contents
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... DATA SHEET SAA7188A Digital Video Encoder (DENC2-M) Preliminary specification Supersedes data of 1995 Sep 21 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1996 Jul 08 ...
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... Down-mode of DACs CVBS and S-Video output simultaneously PLCC68 package. GENERAL DESCRIPTION The SAA7188A encodes digital YUV video data bytes NTSC, PAL CVBS or S-Video signal. The circuit accepts CCIR compatible YUV data with 720 active pixels per line multiplexed formats, e ...
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... XTALO Fig.1 Block diagram. 3 Preliminary specification V DDA1 V refH V DDA4 V DDD1 to V DDD3 17,37,67 A OUTPUT INTERFACE D 8 SAA7188A 8 SYNC CLK LLC CDIR RCV2 CREF RCV1 SAA7188A VERSION SOT188-2 to 48,50, 54,56 53 CVBS CHROMA 52 V SSA 46 V refL MBG266 ...
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... On-Screen Display data. This is the index for the internal OSD look-up table. OSD2 digital ground 5 SSD5 CDIR 36 Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC and CREF are generated by the internal crystal oscillator digital supply voltage 2 DDD2 1996 Jul 08 DESCRIPTION 4 Preliminary specification SAA7188A ...
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... Select MPU interface input HIGH, the parallel MPU interface is active, otherwise the 2 I C-bus interface will be used. 1996 Jul 08 DESCRIPTION 2 C-bus serial clock input. 2 C-bus serial data input/output. 2 C-bus slave address select pin. LOW: slave address = 88h, HIGH = 8Ch. 5 Preliminary specification SAA7188A . DDA ...
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... SEL_MPU 68 V SSD1 1 2 DP4 3 DP5 DP6 4 DP7 5 6 RCV1 RCV2 7 V SSD2 8 9 VP0 1996 Jul 08 SAA7188A Fig.2 Pin configuration. 6 Preliminary specification SAA7188A 43 RTCI V SSD6 42 41 XTALI 40 XTALO 39 CREF 38 LLC 37 V DDD2 36 CDIR V SSD5 35 34 OSD2 33 OSD1 32 OSD0 KEY ...
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... Optionally, the OSD colour look-up tables located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving e.g. a colour bar test pattern generator without need for an external data source. The colour bar function is only under software control. 7 Preliminary specification SAA7188A 2 C-bus or 8-bit MPU ...
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... Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of DENC2-M runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. 8 Preliminary specification SAA7188A 15 with respect ...
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... Cb-Y-Cr data on the VP lines, or the 16-bit DTV2 format with the Y signal on the VP lines and the UV signal on the DP port. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. 9 Preliminary specification SAA7188A 2 C-bus control), ...
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... FORMAT Preliminary specification SAA7188A CODE straight binary straight binary straight binary ...
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... Philips Semiconductors Digital Video Encoder (DENC2-M) 1996 Jul 08 11 Preliminary specification SAA7188A ...
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... Philips Semiconductors Digital Video Encoder (DENC2-M) 1996 Jul 08 12 Preliminary specification SAA7188A ...
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... Selects CCIR 656 compatible format lines Cb, Y, Cr). Default after reset. Data from input ports is encoded. Default after reset. Colour bar with programmable colours (entries of OSD_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7. 13 Preliminary specification SAA7188A ACK -------- DATA n DESCRIPTION DESCRIPTION ...
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... DESCRIPTION CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) nominal. nominal. 14 Preliminary specification SAA7188A INDEX (note 2) OSDV 0 (00H) 0 (00H) 18 (12H) 14 (0EH) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) ...
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... IRE BLNNL = 0 BLNNL = 63 (3FH) 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. 15 Preliminary specification SAA7188A REMARKS output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal REMARKS ...
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... IRE including 7.5 IRE set-up of black; default after reset PAL switch phase is nominal; default after reset PAL switch phase is inverted compared to nominal DACs in normal operational mode; default after reset DACs forced to lowest output voltage 16 Preliminary specification FUNCTION DESCRIPTION SAA7188A ...
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... FSC = 569408543 (21F07C1FH). = 1728 FSC = 705268427 (2A098ACBH). LLC 17 Preliminary specification REMARKS (1) nominal (2) nominal (3) nominal (4) nominal control from SAA7151B digital colour decoder not supported in current version, do not use REMARKS FSC3 = most significant byte 32 2 FSC0 = least significant byte SAA7188A ...
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... Table 20 Logic levels and function of MODIN DATA BYTE MODIN1 MODIN0 1996 Jul 08 DESCRIPTION DESCRIPTION unconditionally from MP port from MP port, if pin SEL_ED = HIGH; otherwise from VP port unconditionally from VP port from VP port, if pin SEL_ED = HIGH; otherwise from MP port 18 Preliminary specification SAA7188A FUNCTION ...
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... RCV1; see Table 22 AS OUTPUT AS INPUT FSEQ FSEQ DESCRIPTION 19 Preliminary specification DESCRIPTION FUNCTION Vertical Sync each field; default after reset Frame Sync (odd/even) Field Sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) not applicable SAA7188A ...
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... VTRIG = (1FH) vertical blanking is defined by programming of FAL and LAL vertical blanking is forced automatically at least during field synchronization and equalization pulses; note 1 selects the phase reset mode of the colour subcarrier generator; see Table 28 20 Preliminary specification FUNCTION FUNCTION DESCRIPTION SAA7188A ...
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... LAL = 0 coincides with the first field synchronization pulse S UBADDRESSES In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. 1996 Jul 08 no reset reset every two lines reset every eight fields reset every four fields DESCRIPTION DESCRIPTION DESCRIPTION 21 Preliminary specification SAA7188A FUNCTION ...
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... FSQ State of the internal field sequence counter. Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH. 1996 Jul VER2 VER1 VER0 CCRDO CCRDE DESCRIPTION 22 Preliminary specification SAA7188A DATA BYTE FSQ2 FSQ1 D0 FSQ0 ...
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... SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 1996 Jul 08 ( Fig.3 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 Fig.4 Chrominance transfer characteristic 2. 23 Preliminary specification 10 12 MBE735 1.2 f (MHz) 1.6 SAA7188A MBE737 14 f (MHz) ...
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... CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0. handbook, halfpage CCRS1 = 0; CCRS0 = 0. 1996 Jul 08 (4) (2) (3) ( Fig.5 Luminance transfer characteristic (dB Fig.6 Luminance transfer characteristic 2. 24 Preliminary specification MBE736 6 f (MHz) SAA7188A MBE738 14 f (MHz) ...
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... I/Os at high impedance note 2 note 2 note LOW or HIGH during acknowledge note 3 note 4 LLC note 3 note 3 25 Preliminary specification CONDITIONS MIN. 4.5 4.75 0.5 2.0 2.4 0 2.4 2.6 0.5 3 SAA7188A MAX. UNIT 5.5 V 5.25 V 170 +0 0.5 V DDD V + 0.5 V DDD 0 0.5 V DDD ...
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... CREF in output mode 26 Preliminary specification SAA7188A MAX. UNIT MHz 6 + 1.5 +20% fF 3.5 +20 ...
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... dmax OD LLC LLC after data is valid. = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output DDA 27 Preliminary specification SAA7188A MIN. MAX. 1 directly proportional to the deviation MHz. LLC LLC ...
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... T LLC t HIGH t HD; DAT LLC t HIGH t HD; DAT t f valid not valid HD; DAT valid not valid Fig.7 Clock data timing. Y(0) Y(1) Cb(0) Cr(0) Fig.8 Digital TV timing. 28 Preliminary specification valid valid Y(2) Y(3) Cb(2) Cr(2) SAA7188A 2.6 V 1.5 V 0.6 V 2.4 V 1.5 V 0.8 V 2.0 V 0.8 V 2.4 V 0.6 V MBE742 Y(4) Cb(4) MBE739 ...
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... Reserved bits: 236 with 50 Hz systems; 233 with 60 Hz systems. 1996 Jul 08 4 bits reserved HPLL FSCPLL increment increment 0 21 valid sample Y) line inverted. Fig.9 RTCI timing. 29 Preliminary specification SAA7188A 5 bits sequence reserved bit (1) 0 invalid 8/LLC MBG270 sample reserved (2) ...
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... D DTACK 1996 Jul RWS ACS Fig.10 MPU interface timing (read cycle RWS ACS Fig.11 MPU interface timing (write cycle). 30 Preliminary specification RWH CSD t DAT MBG268 RWH CSD t DAT MBG269 SAA7188A ...
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... Philips Semiconductors Digital Video Encoder (DENC2-M) APPLICATION INFORMATION 1996 Jul 08 31 Preliminary specification SAA7188A pagewidth full handbook, ...
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... detail max. 25.27 1.22 1.44 0.51 0.18 0.18 25.02 1.07 1.02 0.995 0.048 0.057 0.020 0.007 0.007 0.004 0.985 0.042 0.040 EUROPEAN PROJECTION SAA7188A SOT188 (1) ( max. max. 0.10 2.16 2. 0.085 0.085 ISSUE DATE 92-11-17 95-03-11 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 33 Preliminary specification SAA7188A ...
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... I Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jul components conveys a license under the Philips’ system provided the system conforms to the I 34 Preliminary specification SAA7188A 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Digital Video Encoder (DENC2-M) 1996 Jul 08 NOTES 35 Preliminary specification SAA7188A ...
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... Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7188A_2 June 26, 1996 11:51 am Date of release: 1996 Jul 08 Document order number: SCA50 9397 750 00944 ...