MC68HC11E0 Motorola, MC68HC11E0 Datasheet - Page 52

• Manufacturer Part Number: MC68HC11E0
• Description: (MC68HC711E Series) M68HC11E Series Programming Reference Guide
• Manufacturer: Motorola

M68HC11ERG/AD
Timer Interrupt Mask Register 1 (TMSK1)
Timer Interrupt Mask Register 2 (TMSK2)
52
OC1I–OC4I — Output Compare x Interrupt Enable
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
IC1I–IC3I — Input Capture x Interrupt Enable
TOI — Timer Overflow Interrupt Enable
RTII — Real-Time Interrupt Enable
PAOVI — Pulse Accumulator Input Edge Interrupt Enable
PAII — Pulse Accumulator Input Edge Interrupt Enable
Bits [3:2] — Unimplemented
PR[1:0] — Timer Prescaler Select
Address: $1022
Address: $1024
Reset:
Reset:
Read:
Read:
Write:
Write:
M68HC11E Series Programming Reference Guide
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware
interrupt sequence is requested.
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable
bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt
sequence is requested.
Always reads 0
In normal modes, PR1 and PR0 can only be written once, and the write must
occur within 64 cycles after reset.
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to 1
0 = PAOVF interrupts disabled
1 = Interrupt requested when PAOVF is set to 1
0 = PAIF interrupts disabled
1 = Interrupt requested when PAIF is set to 1
OC1I
Bit 7
Bit 7
TOI
0
0
PR1
= Unimplemented
0
0
1
1
OC2I
RTII
6
0
6
0
PAOVI
OC3I
5
5
0
0
PR0
0
1
0
1
OC4I
PAII
4
0
4
0
I4/O5I
3
0
3
0
Prescaler
÷ 16
÷ 1
÷ 4
÷ 8
IC1I
2
0
2
0
PR1
IC2I
1
0
1
0
MOTOROLA
Bit 0
Bit 0
PR0
IC3I
0
0