MT35 ZARLINK [Zarlink Semiconductor Inc], MT35 Datasheet
MT35
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MT35 Summary of contents
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... Zarlink evaluation kits include application board, TNIM and supporting software based on industry standard operating systems. Device drivers are also available enabling rapid product development and reduction in time to market. Description MT352 is a superior Orthogonal Frequency Division Multiplex (COFDM) television demodulator that is both Nordig II and DVB (as defined in ETS 300 744 specification) compliant ...
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... Blind acquisition mode enables automatic detection of all OFDM signal parameters, including mode, guard and spectral inversion. The frequency capture range is sufficient to compensate for the combined offset introduced by the tuner and broadcaster. The device is packaged pin LQFP and consumes less than 220 mW of power. MT352 MT352 CG ∆ YYWW*W • Pin 1 Corner ...
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... CLK2/GPP0 36 DATA2/GPP1 42 AGC1 41 AGC2/GPP2 43 GPP(3) 9 RESET 27 OSCMODE 26 PLLTEST Analog inputs 30 VIN 31 VIN Supply pins MT352 Description I/O MPEG packet start O MPEG data valid O CMOS Tristate MPEG data bus O MPEG clock out O Block error O MPEG clock in I CMOS Status output O Interrupt output O Open drain ...
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... PLLVDD 22 PLLGND 7, 19, 37, 39, 59, 64 CVDD 2, 13, 45, 54, VDD 14, 20, 25, 38, GND 40, 46, 55 AVDD 29, 32 AGND 33 DVDD 34 DGND MT352 Description I/O PLL supply S S Core logic power S I/O ring power S Core and I/O ground S ADC analog supply S S ADC digital supply Zarlink Semiconductor Inc ...
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... Data Output Header Format 3.3.2 MPEG data output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3.1 MOCLKINV = 3.3.3.2 MOCLKINV = 4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MT352 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - MPEG Output Data Waveforms Figure 9 - MPEG Timing - MOCLKINV = Figure 10 - MPEG Timing - MOCLKINV = Figure 11 - Crystal Oscillator Circuit Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MT352 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application Table 2 - Timing of 2-Wire Bus Table 3 - MOCLKINV = Table 4 - MDOSWAP = Table 5 - MDOSWAP = MT352 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description A functional block diagram of the MT352 OFDM demodulator is shown in Figure 3. This accepts an IF analogue signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchronization operations are all digital and there are no analogue control loops except the AGC. The frequency capture range is large enough for all practical applications ...
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... This is one of the features of MT352 used to minimize acquisition time. A robust AGC lock mechanism is provided and the other parts of the MT352 begin to acquire only after the AGC has locked. Two AGC control outputs are available, one to drive an RF amplifier and the other to control an IF amplifier. The parameters for both loops are programmable ...
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... MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is programmed in a MT352 register (defaults are for 20.48 MHz sampling and 8 MHz OFDM). The clock recovery phase locked loop in the MT352 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock. ...
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... It may also detect frames with more than eight byte errors. In addition to efficiently performing this decoding function, the Reed-Solomon decoder in MT352 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can be used to compute the post-Viterbi BER ...
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... MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the MT352 with a clock provided by the user. ...
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... Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application When the MT352 is powered up, the RESET pin 28 should be held low for at least 50ms after VDD has reached normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address ...
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... Examples of 2-Wire Bus Messages KEY: Italics Write operation - as a slave receiver: S DEVICE ADDRESS Read operation - MT352 as a slave transmitter: S DEVICE ADDRESS Write/read operation with repeated start - MT352 as a slave transmitter: S DEVICE W A RADD ADDRESS 3.2.3 Primary 2-Wire Bus Timing Where Start Sr = Restart, i.e., start without stopping first. ...
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... Rise time of both CLK and DATA signal. Fall time of both CLK and DATA signals, (100 pF to ground) Set-up time for a STOP condition Note 1. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation. 3.3 MPEG 3.3.1 Data Output Header Format MT352 f CLK t BUFF t HD;STA t ...
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... MPEG Output Timing Maximum delay conditions: VDD = 3.0 V, CVDD = 1.62 V, Tamb = 70 Minimum delay conditions: VDD = 3.6 V, CVDD = 1.98 V, Tamb = 0 MOCLK frequency = 61.44 MHz. MT352 Figure 8 - MPEG Output Data Waveforms o C, Output load = Output load = Zarlink Semiconductor Inc ...
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... The setup time is due to the delay on MOSTRT, MOVAL and BKERR. MDO[0] is faster since it uses a stronger output driver cell. 3.3.3.2 MOCLKINV = 0 MDOSWAP = 0 Parameter Data output delay t D Setup Time t SU Hold Time t H MT352 Minimum Delay Conditions 0 Table 3 - MOCLKINV = 1 Figure 9 - MPEG Timing - MOCLKINV = 1 Maximum Delay Conditions 1.5 ns Table 4 - MDOSWAP = 0 17 Zarlink Semiconductor Inc ...
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... The hold time is due to the fast output on MDO[0]. If MDOSWAP is set to 1 the data output is on MDO[7] which has a slower driver. This improves the hold time: MDOSWAP = 1 Parameter Data output delay t D Setup Time t SU Hold Time t H MT352 Maximum Delay Conditions Table 5 - MDOSWAP = 1 Figure 10 - MPEG Timing - MOCLKINV = 0 18 Zarlink Semiconductor Inc. Data Sheet Minimum Delay Conditions 0 ...
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... Storage temperature Operating ambient temperature Junction temperature Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. MT352 Symbol Min. periphery VDD 3· ...
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... VDD+0.5 V Input levels 3.0 > VDD > 3.6 -0.5 ≥ Vin ≥ +5.5 V Input levels Input leakage Current 3.0 > VDD > 3.6 Capacitances Input capacitance do not include track Input capacitance MT352 Pins Symbol VDD CVDD IDD- CORE MDO(7:0), MOVAL, VOH MOSTRT, MOCLK, STATUS, BKERR VOL GPP(3:0), DATA1, VOL AGC1, AGC2, IRQ ...
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... Crystal Specification and External Clocking Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Typical load capacitance Drive level Equivalent series resistance C1 MT352 20.4800 MHz ± 25 ppm ± 50 ppm 27 pF 0.4 mW max. <50 Ω XTI XTO XT1 C2 Figure 11 - Crystal Oscillator Circuit 21 Zarlink Semiconductor Inc ...
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... Application Circuit MT352 Figure 12 - Typical Application Circuit 22 Zarlink Semiconductor Inc. Data Sheet ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...