MBM29F016A-12 FUJITSU [Fujitsu Component Limited.], MBM29F016A-12 Datasheet - Page 16

• Manufacturer Part Number: MBM29F016A-12
• Description: 16M (2M X 8) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

16
MBM29F016A
Write Operation Status
Notes: 1. Performing successive read operations from the erase-suspended sector will cause DQ
DQ
Data Polling
In Progress
Exceeded
Time Limits
The MBM29F016A device features Data Polling as a method to indicate to the host that the embedded algorithms
are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will
produce the complement of the data last written to DQ
an attempt to read the device will produce the true data last written to DQ
Algorithm, an attempt to read the device will produce a “0” at the DQ
Erase Algorithm an attempt to read the device will produce a “1” at the DQ
(DQ
Data polling will also flag the entry into Erase Suspend. DQ
mode. Please note that the address of an erasing sector must be applied in order to observe DQ
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector group. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ
enable (OE) is asserted low. This means that the device is driving status information on DQ
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ
7
2. Performing successive read operations from any address will cause DQ
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
7
) is shown in Figure 18.
“1” at the DQ
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
2
bit. However, successive reads from the erase-suspended sector will cause DQ
Status
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
-70/-90/-12
Table 7
Hardware Sequence Flags
7
. Upon completion of the Embedded Program Algorithm,
7
will switch “0” to “1” at the start of the Erase Suspend
7
Data
DQ
DQ
DQ
DQ
DQ
may change asynchronously while the output
0
1
0
7
output. Upon completion of the Embedded
7
7
7
7
7
(Note 2)
7
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
output. The flowchart for Data Polling
7
Data
DQ
. During the Embedded Erase™
1
6
6
to toggle.
Data
DQ
0
0
0
0
1
1
1
5
7
at one instant of
Data
DQ
2
0
1
0
0
0
1
0
to toggle.
7
3
in the Erase
2
to toggle.
(Note 1)
(Note 3)
Toggle
Toggle
Data
DQ
N/A
N/A
1
1
1
2
7