AD7476ART-REEL AD [Analog Devices], AD7476ART-REEL Datasheet - Page 10

• Manufacturer Part Number: AD7476ART-REEL
• Description: 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: AD [Analog Devices]

AD7476/AD7477/AD7478
CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, fast, micropower, single-supply ADCs. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7476/AD7477/AD7478
are capable of throughput rates of 1 MSPS when provided with
a 20 MHz clock.
The AD7476/AD7477/AD7478 provide the user with an on-chip,
track-and-hold ADC, and a serial interface housed in a tiny
6-lead SOT-23 package, which offers the user considerable
space saving advantages over alternative solutions. The serial
clock input accesses data from the part and also provides the
clock source for the successive-approximation ADC. The analog
input range is 0 V to V
for the ADC, nor is there a reference on-chip. The reference for
the AD7476/AD7477/AD7478 is derived from the power supply
and thus gives the widest dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down option
to save power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 are successive-approximation
analog-to-digital converters based around a charge redistribution
DAC. Figures 2 and 3 show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on V
When the ADC starts a conversion (see Figure 3), SW2 will open
and SW1 will move to Position B, causing the comparator to
become unbalanced. The Control Logic and the Charge Redistri-
bution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 4 and 5 show the ADC transfer function.
V
V
IN
IN
SW1
SW1
IN
AGND
AGND
.
Figure 3. ADC Conversion Phase
Figure 2. ADC Acquisition Phase
A
B
A
B
CONVERSION
ACQUISITION
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
V
PHASE
V
PHASE
DD
DD
/2
/2
DD
. An external reference is not required
SW2
SW2
COMPARATOR
COMPARATOR
REDISTRIBUTION
REDISTRIBUTION
CHARGE
CHARGE
CONTROL
CONTROL
DAC
DAC
LOGIC
LOGIC
–10–
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values (i.e.,
1/2 LSB, 3/2 LSB, and so on). The LSB size for the AD7476
is V
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 4.
For the AD7478, designed code transitions occur midway between
successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on).
The LSB size for the AD7478 is V
characteristic for the AD7478 is shown in Figure 5.
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7476/
AD7477/AD7478. V
such, V
input range of 0 V to V
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477
will be followed by two trailing zeros. The 8-bit result from
the AD7478 will be followed by four trailing zeros.
Figure 4. Transfer Characteristic for the AD7476/AD7477
DD
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
/4096 and the LSB size for the AD7477 is V
DD
Figure 5. Transfer Characteristic for AD7478
should be well decoupled. This provides an analog
0V
0V
1LSB
0.5LSB
REF
DD
is taken internally from V
. The conversion result is output in a
ANALOG INPUT
ANALOG INPUT
DD
1LSB = V
/256. The ideal transfer
1LSB = V
1LSB = V
DD
DD
DD
V
V
/256 (AD7478)
DD
/4096 (AD7476)
/1024 (AD7477)
DD
–1LSB
–1.5LSB
DD
DD
/1024. The
and as
REV. D