ICS1890Y ICST [Integrated Circuit Systems], ICS1890Y Datasheet
ICS1890Y
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ICS1890Y Summary of contents
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Status Idle Parallel Detected Parallel Detection Failure Ability Matched Acknowledge Match Failure Acknowledge Matched Consistency Match Failure Consistency Matched Auto-Negotiation Completed Successfully Progress Monitor Status Bits A-N Complete Bit ...
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Code Symbol Meaning 3210 0 Data 0 1 Data 1 2 Data 2 3 Data 3 4 Data 4 5 Data 5 6 Data 6 7 Data 7 I Idle undefined J SSD K SSD T ESD undefined R ...
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Resistance (Ohm/m) v. Freq. (MHz 0 100 ...
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Cable Attenuation (dB) v. Freq. (MHz 0 100 typical worst case ...
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Bit Definition 15 Reset no effect 14 Loopback disable loop back mode 13 Data Rate 10 Mb/s operation 12 Auto-Negotiation Enable disable Auto-Negotiation 11 Power-Down normal mode 10 Isolate no effect 9 Restart Auto-Negotiation no effect 8 Duplex Mode half ...
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Bit Definition 15 100Base-T4 always 0 TX full duplex not 14 100Base-TX Full Duplex supported TX half duplex not 13 100Base-TX Half Duplex supported 10 full duplex not 12 10Base-T Full Duplex supported 10 half duplex not 11 10Base-T Half ...
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Bit Definition 15 OUI bit OUI bit OUI bit OUI bit OUI bit OUI bit OUI ...
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Bit Definition 15 OUI bit OUI bit OUI bit OUI bit OUI bit OUI bit Manufacturer’s ...
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Bit Definition 15 Next Page 14 Reserved by IEEE 13 Fault Indication to link partner 12 Technology Ability Field bit A7 11 Technology Ability Field bit A6 10 Technology Ability Field bit A5 9 TAF bit A4: 100Base-T4 Capability TAF ...
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Bit Definition 15 Next Page 14 Reserved by IEEE 13 Remote Fault Technology Ability Field 12 bit A7 Technology Ability Field 11 bit A6 Technology Ability Field 10 bit A5 TAF bit A4: 100Base-T4 9 Capability TAF A3: 100Base-TX 8 ...
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Bit Definition 15 Reserved by IEEE 14 Reserved by IEEE 13 Reserved by IEEE 12 Reserved by IEEE 11 Reserved by IEEE 10 Reserved by IEEE 9 Reserved by IEEE 8 Reserved by IEEE 7 Reserved by IEEE 6 Reserved ...
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Bit Definition 15 Command Register Override 14 Reserved for ICS 13 Reserved for ICS 12 Reserved for ICS 11 Reserved for ICS 10 PHY address bit 4 9 PHY address bit 3 8 PHY address bit 2 7 PHY address ...
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Bit Definition 15 Data Rate 14 Duplex Auto-Negotiation Progress 13 Monitor bit 2 Auto-Negotiation Progress 12 Monitor bit 1 Auto-Negotiation Progress 11 Monitor bit 0 10 Receive Signal Error 9 PLL Lock Error 8 False Carrier Detect 7 Invalid Symbol ...
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Bit Definition 15 Reserved for ICS Read unspecified 14 Polarity Reversed polarity normal 13 Reserved for ICS Read unspecified 12 Reserved for ICS Read unspecified 11 Reserved for ICS Read unspecified 10 Reserved for ICS Read unspecified 9 Reserved for ...
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Bit Definition 15 Node/Repeater Mode Node Mode 14 Hardware/Software Priority Hardware Priority Link Partner Supports 13 unknown Remote Fault 12 Reserved for ICS Read unspecified 11 Reserved for ICS Read unspecified Transmitted Remote Fault 10 RF bit in transmitted LCW=0 ...
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Signal Meaning TXCLK* Transmit Clock TXEN* Transmit Enable TXD3* Transmit Data 3 TXD2* Transmit Data 2 TXD1* Transmit Data 1 TXD0* Transmit Data 0 TXER* Transmit Error RXCLK* Receive Clock RXDV* Receive Data Valid RXD3 Receive Data 3 RXD2* Receive ...
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NOD/REP ITCLS 0 NOD ( REP (1) 1 Latching Clock REF_IN TXCLK TXCLK REF_IN ...
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Digital Domain Transmit Domain 16 VDD 41 VDD 8 VDD 18 VDD 40 VSS 7VSS 17 VSS 54 VDD 56 VDD 25 VDD 51 VSS 55 VSS 29 VSS 57 VDD 63 VSS Receive Domain ...
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PIN PIN NAME NUMBER 1 NOD/REP 2 10/100SEL 3 10TCSR 4 100TCSR 5 TP_TX 6 TP_TX- 7 VSS 8 VDD 9 TPTRI 10 TP_RX+ 11 TP_RX- 12 N/C 13 ITCLS~ 14 N/C 15 N/C 16 VDD 17 VSS 18 VDD ...
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PIN PIN NAME NUMBER 33 RXD2* 34 RXD1* 35 RXD0* 36 RXDV* 37 RXCLK* 38 RXER 39 RXTRI 40 VSS 41 VDD 42 TXER* 43 TXCLK* 44 TXEN* 45 TXD0* 46 TXD1* 47 TXD2* 48 TXD3* 49 COL* 50 CRS* ...
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PARAMETER SYMBOL Ambient Operating Temp. VSS Power Supply VDD PARAMETER Crystal Oscillator Frequency* Crystal Oscillator Frequency Tolerance 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value TEST CONDITIONS TA MIN -50 1.4 6.49 510 MIN MAX 0 +70 0.0 0.0 ...
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PARAMETER SYMBOL IC Supply Current I DD PARAMETER TTL Input High Voltage TTL Input Low Voltage TTL Output High Voltage TTL Output Low Voltage TTL Driving CMOS, Output High Voltage TTL Driving CMOS, Output Low Voltage TTL/CMOS Output Sink Current ...
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T# PARAMETER (condition) t1 REF_IN Duty Cycle t2 REF_IN Period MIN TYP MAX UNITS ...
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T# PARAMETER (condition) t1 TXCLK Duty Cycle t2a TXCLK Period (100Base-T/MII Interface) t2b TXCLK Period (10Base-T/MII Interface) t2c TXCLK Period (100Base-T/100M Stream Interface) t2d TXCLK Period (10Base-T/10M Serial Interface) T# PARAMETER (condition) t1 RXCLK Duty Cycle t2a RXCLK Period (100Base-T/MII ...
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T# PARAMETER (condition) t1 TXD, TXEN, TXER Setup to TXCLK rise t2 TXD, TXEN, TXER Hold after TXCLK rise T# PARAMETER (condition) t1 RXD, RXDV, RXER Setup to RXCLK rise t2 RXD, RXDV, RXER Hold after RXCLK rise MIN TYP ...
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T# PARAMETER (condition) t1 MDC Minimum High Time t2 MDC Minimum Low Time t3 MDC Period t4 MDC rise to MDIO valid t5 MDIO Setup to MDC t6 MDIO Hold after MDC t7 Maximum allowable frequency (50pF Loading) MIN TYP ...
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T# PARAMETER (condition) TP_RX input to 10RD delay t1 (10M Serial Interface) T# PARAMETER (condition) 1st bit of /5/ on TP_RX to /5/ on RXD t1 (10M MII) MIN TYP MAX 15 - 16.5 MIN TYP MAX 18 - 19.5 ...
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T# PARAMETER (condition) 10TD in to TP_TX out delay t1 (10M Serial Interface) T# PARAMETER (condition) TXD sampled to MDI Output of 1st bit t1 (10M MII) MIN TYP MAX - 1.5 - MIN TYP MAX - 1.5 - UNITS ...
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T# PARAMETER (condition) t1 TXEN sampled to MDI Output 1st bit of /J/ (MII IF)* t2 TXD sampled to MDI Output of 1st bit (100M Stream IF) MIN TYP MAX UNITS - - 4BT - - 5 bits bits ...
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T# PARAMETER (condition) t1 TXEN sampled to CRS assert t2 TXD sampled to CRS de-assert T# PARAMETER (condition) t1 1st bit of /J/ into TP_RX to /J/ on RXD (100M MII IF) t2 1st bit of /J/ into TP_RX to ...
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T# PARAMETER (condition) t1 1st bit of /J/ into TP_RX to CRS assert* 1st bit of /J/ into TP_RX while transmitting data to t2 COL assert (Half Duplex Mode)* t3 First bit of /T/ into TP_RX to CRS de-assert** First ...
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T# PARAMETER (condition) t1 VDD to 4.5V to Reset Complete T# PARAMETER (condition) t1 RESET active to device isolation and initialization t2 Minimum RESET pulse width t3 RESET released to device ready MIN TYP MAX - - 20 MIN TYP ...
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T# PARAMETER (condition) COL Heartbeat assertion delay from TXEN de-assertion t1 (10Base-T Half Duplex) t2 COL Heartbeat assertion duration (10Base-T Half Duplex) T# PARAMETER (condition) t1 Jabber activation time (10Base-T Half Duplex) t2 Jabber deactivation time (10Base-T Half Duplex) MIN ...
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T# PARAMETER (condition) t1 Normal Link Pulse Width (10Base-T) t2 COL Heartbeat assertion duration (10Base-T Half Duplex) T# PARAMETER (condition) t1 Clock/Data pulse width t2 Clock pulse to Data pulse timing t3 Clock pulse to Clock pulse t4 FLP Burst ...
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T# PARAMETER (condition) t1 Ideal data recovery window t2 Actual data recovery window t3 Data recovery window truncation t4 SD assert to data acquired MIN TYP MAX UNITS - - 100 ...
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DIMENSION NAME DIMENSIONS Full Package Height A Package Standoff A Package Thickness A Tip-to-Tip Width D Body Width D Tip-to-Tip Width E Body Width E1 Footlength L Lead Pitch Lead Width w/Plate B Lead Height w/Plate LEAD COUNT (N) 64L ...