ICS200 ICST [Integrated Circuit Systems], ICS200 Datasheet
ICS200
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ICS200 Summary of contents
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... Code) and/or VITC (Vertical Interval Time Code) formats and MTC (MIDI Time Code) translation. Taking its input from composite video, S-Video audio track, the ICS2008B can read SMPTE time code in VITC and LTC formats. Time code output formats are LTC and VITC. All are available simultaneously. A UART is provided for the user to support MTC or tape transport control ...
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... LTCOUT 1 LFC 2 XTAL2 3 XTAL1 4 AVDD 5 AVSS 6 COUT 7 YOUT ICS2008B Rev D 4/05/ LTCOUT 7 LFC 8 XTAL2 9 10 XTAL1 11 AVDD AVSS 12 13 COUT 14 YOUT ...
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... Write Enable (active low) I SMPTE port chip select (active low) I UART chip select (active low) I Master reset (active high) I/O Bi-directional data bus O Interrupt Request (active high) P Analog Analog Ground P Digital Digital 2008 2008B ICS2008 3 ICS2008B DESC RIPTI ON ICS2008B Rev D 4/05/05 ...
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... ICS2008B chip. It also describes how those registers can be utilized by the software to facilitate specific application services. Hardware Environments The ICS2008B operates as a peripheral to a processor such single chip microprocessor. Many of the real time requirements are satisfied by double buffering both incoming and outgoing time codes. ...
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... MIDI time code messages. Processor Interface The ICS2008B supports standard microprocessor interfaces and busses, such as the PC bus, to allow access to six control/ status and data registers. These six registers are organized into two groups, one set of four for SMPTE control and the other set of two for direct UART port control ...
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... SYNC source. FRAME & FIELD — The hardware SYNC separator detects ICS2008B Rev D 4/05/05 the field and frame from the selected video input. The even/ odd fields are identified by a 1/0 in bit 6. Bit 7, FRAME, is valid for PAL video after line 6 ...
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... VITC Write Enable – Enables the output of VITC code on the specified line. 7 ICS2008B – (Frame) – (Seconds) – (Minutes) – (Hours ICS2008B Rev D 4/05/05 ...
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... NOCODE — This bit is set when a framing error occurs in the VITC code, i.e. not all the bits of the code were received by the time the end of the video line occurred. Both CRCERR and NOCODE must be zero to qualify a VITC code. ICS2008B Rev D 4/05/05 Video Control Register IR32 IR32 ...
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... C: 0dB 1: 5: -21dB 3dB 2: 6: -18dB 6dB 3: 7: -15dB 9dB Reserved DIVIDER VALUE 30 Hz BA6h BA9h 25 Hz DFBh 24 Hz E90h LTC Bit Time (write only) IR36 – (low byte) IR37 – (high byte) ICS2008B Rev D 4/05/05 ...
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... The 100 kHz input is actually 100.126 kHz the crystal frequency divided by 143. RUN — This bit starts and stops the timer. When set to one, the timer is running. When set to zero, the timer is stopped. ICS2008B Rev D 4/05/ IR3E Burn-in Window Attributes ...
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... VITC WRITE LINE VITC WRITE LINE VITC READ LINE VITC READ LINE VSYNCSEL VTRES 0 LTXFREE EDGE RATE 0 0 TIMER VALUE (high) WINDOW ATTRIBUTE ICS2008B Rev D 4/05/05 0 GEN_EN BLINK ...
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... RIE — Bit 7, Receive interrupt enable, when set to one, enables the UART to interrupt the processor when the receive buffer is full or a receive overrun has occurred. ICS2008B Rev D 4/05/ RBF — Bit 0, Receive Buffer Full, is set to 1 when read data is available in the UART data register ...
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... Analog VDD Supply Current Digital VDD Supply Current + 0 SYMBOL MIN TYP VIL –0.5 VIH 2.0 IIL CIN VOL VOH 2.4 IOZ 1.0 0.1 –0.3 VDD/3 1.0 2 IDD1 IDD2 13 ICS2008B MAX UNITS 0.8 V VDD+0 0 Vp-p Vp-p VDD+0 Vp-p Vp ICS2008B Rev D 4/05/05 ...
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... Register [1:0] = 00) UART Port Bit Rate (Command Register [1:0] = 01) UART Port Bit Rate (Command Register [1:0] = 10) Notes: 1. This timing parameter must be met for proper operation of indirect register access using auto-increment. FIGURE 3 — Host Processor Bus Timing ICS2008B Rev D 4/05/05 SYMBOL MIN TYP t 20 ACS t ...
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... LTCIN – should be capacitively coupled to the ground reference of that source. If the LTC source is digital, set the LTCIN – to the desired threshold, and connect the digital source to LTCIN+. 15 ICS2008B Fig Video Output be Fig Self Biased Inputs ICS2008B Rev D 4/05/05 ...
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... This makes the ICS2008B flexible enough for a broad range of ap- plications without making the processing requirements on the host system too great. ...
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... VITC receive and generate operations to be com- plete before processing VITC. The VLOCK bit in the SMPTE1 register indicates whether the ICS2008B is genlocked to the selected video source. Without the VLOCK status set to one, no VITC read will occur. When VLOCK is set to one and the control registers are prop- erly initialized, VITC data are received a byte at a time from the video signal and written to the VITC Read registers ...
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... ICS2008B PLCC 44-PIN PACKAGE All Dimensions in Inches ICS2008B Rev D 4/05/ ...
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... ° 7 ° ICS2008B Rev D 4/05/05 ...
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... ICS2008B Document Revision History Rev A (First Release) Started with ICS2008A Rev D Source Document General cleanup for readability. Rev B Correct C2 pin number in Pin Description (pg 3) Call out tieing LFC pin high in Pin Description (pg 3) Added Document Revision History. (pg 20) Added Corporate Contact Information (pg 21) Rev C Added information to PLCC and TQFP Package Diagrams (page 18 & ...
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... Integrated Circuit Systems, Inc. Corporate Headquarters:2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone: Fax: San Jose Operations: 525 Race Street San Jose, CA 95126-3448 Telephone: Fax: Web Site: http://www.icst.com 610-630-5300 610-630-5399 408-297-1201 408-925-9460 21 ICS2008B ICS2008B Rev D 4/05/05 ...