MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 45

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

DQML, DQMH
TIMING PARAMETERS
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
*CAS latency indicated in parentheses.
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
BA0, BA1
DQM /
CKE
CLK
A10
DQ
2. x16: A9 and A11 = “Don’t Care”
3. READ command not allowed else
x8: A11 = “Don’t Care”
t CKS
t CMS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
t AS
t AS
t AS
7
ACTIVE
T0
ROW
ROW
BANK
-7E
t CMH
t CKH
t AH
t AH
t AH
MAX
5.4
5.4
t RCD
t RAS
t RC
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
T1
NOP
-75
SINGLE READ – WITH AUTO PRECHARGE
MAX
5.4
6
t CL
T2
NOP 3
MIN
10
1
2
3
3
8
1
2
t CH
t
RAS would be violated.
-8E
MAX
6
6
T3
NOP 3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
t CMS
45
COLUMN m 2
BANK
T4
READ
t CMH
CAS Latency
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RAS
RC
RCD
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
0.8
1.5
37
60
15
15
1
3
t RP
-7E
120,000
MAX
5.4
5.4
D
T6
OUT
NOP
128Mb: x4, x8, x16
t OH
m
t HZ
1
MIN
0.8
1.5
44
66
20
20
1
3
-75
120,000
MAX
ACTIVE
5.4
ROW
BANK
T7
ROW
6
MIN
50
70
20
20
1
2
1
3
©2001, Micron Technology, Inc.
SDRAM
-8E
120,000
T8
MAX
NOP
DON’T CARE
UNDEFINED
6
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns