54F NSC [National Semiconductor], 54F Datasheet - Page 2

• Manufacturer Part Number: 54F
• Description: Up/Down Binary Counter with Separate Up/Down Clocks
• Manufacturer: NSC [National Semiconductor]

Unit Loading Fan Out
Functional Description
The ’F193 is a 4-bit binary synchronous up down (revers-
ible) counter It contains four edge-triggered flip-flops with
internal gating and steering logic to provide master reset
individual preset count up and count down operations
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state Synchronous switching
as opposed to ripple counting is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line thereby causing all state
changes to be initiated simultaneously A LOW-to-HIGH
transition on the Count Up input will advance the count by
one a similar transition on the Count Down input will de-
crease the count by one While counting with one clock in-
put the other should be held HIGH as indicated in the
Function Table
The Terminal Count Up (TC
(TC
reached the maximum count state 15 the next HIGH-to-
LOW transition of the Count Up Clock will cause TC
LOW TC
effectively repeating the Count Up Clock but delayed by
two gate delays Similarly the TC
the circuit is in the zero state and the Count Down Clock
goes LOW Since the TC outputs repeat the clock wave-
forms they can be used as the clock input signals to the
next higher order circuit in a multistage counter
The ’F193 has an asynchronous parallel load capability per-
mitting the counter to be preset When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW informa-
tion present on the Parallel Data input (P
into the counter and appears on the outputs regardless of
the conditions of the clock inputs A HIGH signal on the
Master Reset input will disable the preset gates override
both clock inputs and latch each Q output in the LOW state
Pin Names
CP
CP
MR
PL
P
Q
TC
TC
0
0
–P
U
D
–Q
D
U
D
) outputs are normally HIGH When the circuit has
3
3
U
will stay LOW until CP
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
TC
TC
U
D
e
e
Q
Q
0
0
Q
Q
1
1
U
) and Terminal Count Down
Q
Q
Description
D
2
2
U
output will go LOW when
goes HIGH again thus
Q
Q
3
3
CP
CP
0
U
D
– P
3
) is loaded
U
to go
2
HIGH LOW Output I
If one of the clock inputs is LOW during and after a reset or
load operation the next LOW-to-HIGH transition of that
clock will be interpreted as a legitimate signal and will be
counted
H
L
X
State Diagram
50 33 3
50 33 3
50 33 3
1 0 3 0
1 0 3 0
1 0 1 0
1 0 1 0
1 0 1 0
e
e
e
U L
MR
e
H
L
L
L
L
LOW Voltage Level
HIGH Voltage Level
Immaterial
LOW-to-HIGH Clock Transition
54F 74F
20 A
20 A
20 A
20 A
20 A
PL
b
b
b
X
H
H
H
L
Input I
1 mA 20 mA
1 mA 20 mA
1 mA 20 mA
b
b
b
b
b
IH
OH
1 8 mA
1 8 mA
0 6 mA
0 6 mA
0 6 mA
CP
Function Table
X
X
H
H
I
IL
U
I
OL
CP
H
H
X
X
D
Reset (Asyn )
Preset (Asyn )
No Change
Count Up
Count Down
Mode
TL F 9497– 5