AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 31

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5
5.1
The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers to
register addresses that are accessed via x86 IO instructions such as IN and OUT. PCI configuration space is typically
accessed via PCI-defined IO cycles to CF8h and CFCh in the host. There is also memory space and indexed address
space in the IC.
5.1.1
The address space for PCI configuration registers is broken up into busses, devices, functions, and, offsets, as defined
by the PCI specification. Configuration registers within the IC are accessed by type 0 configuration cycles. The
IDSEL pin specifies the IC as the targeted device. The function number is mapped into bits[10:8] of the
configuration address. The offset is mapped to bits[7:2] of the configuration address.
5.1.2
Each register location has an assigned mnemonic that specifies the address space and offset. These mnemonics start
with two to four characters that identify the space followed by characters that identify the offset within the space.
Register fields within register locations are also identified with a name or bit group in brackets following the register
location mnemonic. For example, the ACPI sleep type register field, which is located at offset 04h of PMxx space,
bits10, 11, and 12, is referenced as PM04[SLP_TYP] or PM04[12:10].
PCI configuration spaces are referenced with mnemonics that takes the form of C[4:0]A[FF:0], where the first
bracket contains function number and the last bracket contains the offset.
PCI configuration spaces.
Function
Register Overview
0
1
2
3
4
Registers
Configuration Space
Register Naming And Description Conventions
Mnemonic Function
C0Axx
C1Axx
C2Axx
C3Axx
C4Axx
PCI-ISA/LPC bridge
IDE controller
Not used
System management registers
USB controller
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
31