ICS8521 ICST [Integrated Circuit Systems], ICS8521 Datasheet

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ICS8521

Manufacturer Part Number
ICS8521
Description
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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G
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulseson the outputs during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
B
8521BY
HiPerClockS™
,&6
CLK_SEL
LOCK
ENERAL
CLK_EN
nPCLK
PCLK
nCLK
CLK
D
The ICS8521 is a low skew, 1-to-9 3.3V Differ-
ential-to-LVHSTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS8521 has two
selectable clock inputs. The CLK, nCLK pair can
IAGRAM
D
0
1
ESCRIPTION
D
LE
Q
www.icst.com/products/hiperclocks.html
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
1
F
P
D
9 LVHSTL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency up to 500MHz
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.8ns (maximum)
V
3.3V core, 1.8V output operating supply voltages
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
EATURES
IN
IFFERENTIAL
OH
CLK_SEL
= 1.2V (maximum)
A
CLK_EN
nPCLK
PCLK
SSIGNMENT
nCLK
GND
CLK
V
7mm x 7mm x 1.4mm Package Body
DD
1
2
3
4
5
6
7
8
-
TO
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
9 1 0 1 1 1 2 1 3 1 4 1 5 16
32-Lead LQFP
-LVHSTL F
ICS8521
Y Package
Top View
L
OW
ANOUT
S
ICS8521
KEW
24
23
22
21
20
19
18
17
REV. B JULY 31, 2001
V
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
, 1-
B
DDO
DDO
UFFER
TO
-9

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ICS8521 Summary of contents

Page 1

... G D ENERAL ESCRIPTION The ICS8521 is a low skew, 1-to-9 3.3V Differ- ,&6 ential-to-LVHSTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels ...

Page 2

... www.icst.com/products/hiperclocks.html 2 ICS8521 KEW - -LVHSTL F TO ANOUT . ...

Page 3

... www.icst.com/products/hiperclocks.html 3 ICS8521 KEW - -LVHSTL ANOUT ...

Page 4

... www.icst.com/products/hiperclocks.html 4 ICS8521 KEW - -LVHSTL F TO ANOUT = 0°C 70° ...

Page 5

... www.icst.com/products/hiperclocks.html 5 ICS8521 KEW - -LVHSTL ANOUT = 0°C 70° ...

Page 6

... IGURE UTPUT OAD EST IRCUIT DD V Cross Points IGURE IFFERENTIAL NPUT EVEL tsk( IGURE UTPUT KEW www.icst.com/products/hiperclocks.html 6 ICS8521 KEW - -LVHSTL ANOUT UFFER SCOPE Qx V CMR REV. B JULY 31, 2001 -9 TO ...

Page 7

... UTPUT ISE AND IGURE ROPAGATION ELAY Pulse Width t PERIOD t PW odc = t PERIOD odc & t IGURE P ERIOD www.icst.com/products/hiperclocks.html 7 ICS8521 KEW - -LVHSTL ANOUT 80 20 ALL IME REV. B JULY 31, 2001 -9 TO UFFER ...

Page 8

... IGURE 8521BY D IFFERENTIAL A I PPLICATION NFORMATION NPUT TO CCEPT INGLE CLK_IN + V_REF - C1 R2 0.1uF INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 8 ICS8521 KEW TO - -LVHSTL ANOUT UFFER E L NDED EVELS / NPUT REV. B JULY 31, 2001 -9 ...

Page 9

... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...

Page 10

... Pd_H = (1.2V/ (2V - 1.2V) = 19.2mW Pd_L = (0.4V/ (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW 8521BY D IFFERENTIAL LVHSTL D C RIVER IRCUIT AND ) – 1.2V DD_MAX – 0.4V DD_MAX www.icst.com/products/hiperclocks.html 10 ICS8521 KEW - -LVHSTL ANOUT V OUT ERMINATION REV. B JULY 31, 2001 -9 TO ...

Page 11

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8521 is: 944 8521BY D IFFERENTIAL R I ELIABILITY ...

Page 12

... ° www.icst.com/products/hiperclocks.html 12 ICS8521 KEW - -LVHSTL F TO ANOUT ° ...

Page 13

... www.icst.com/products/hiperclocks.html 13 ICS8521 KEW - -LVHSTL ANOUT ° ...

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