IS61C3216 ICSI [Integrated Circuit Solution Inc], IS61C3216 Datasheet - Page 6

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IS61C3216

Manufacturer Part Number
IS61C3216
Description
32K x 16 HIGH-SPEED CMOS STATIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet

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IS61C3216
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
6
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1a.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
WC
SCE
AW
HA
SA
PWB
PWE
SD
HD
HZWE
LZWE
(2)
(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min. Max.
10
9
9
1
0
9
7
5
0
1
-10
5
Min. Max.
12
10
10
10
1
0
8
6
0
1
-12
(1,3)
6
(Over Operating Range)
Min. Max.
15
11
11
11
10
1
0
7
0
1
-15
7
Integrated Circuit Solution Inc.
Min. Max.
20
12
12
12
11
1
0
8
0
1
-20
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SR008-0B

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