CY7C1347G-166BZXC CYPRESS [Cypress Semiconductor], CY7C1347G-166BZXC Datasheet

CY7C1347G-166BZXC

Manufacturer Part Number

CY7C1347G-166BZXC

Description

4-Mbit (128K x 36) Pipelined Sync SRAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1347G-166BZXC.pdf (21 pages)

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Cypress Semiconductor Corporation

Document #: 38-05516 Rev. *E

Features

Selection Guide

Note

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

1. For best practice recommendations, refer to the Cypress application note

• Fully registered inputs and outputs for pipelined operation

• 128K x 36 common IO architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in lead-free 100-Pin TQFP, lead-free and non-

• “ZZ” sleep mode option and stop clock option

• Available in industrial and commercial temperature ranges

— 2.6 ns (for 250-MHz device)

interleaved or linear burst sequences

lead-free 119-Ball BGA package and 165-Ball FBGA

package

)

DDQ

)

•

4-Mbit (128K x 36) Pipelined Sync SRAM

198 Champion Court

Pentium

250 MHz

AN1064, SRAM System

325

2.6

Functional Description

The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined

SRAM designed to support zero-wait-state secondary cache

with minimal glue logic. CY7C1347G IO pins can operate at

either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant

when V

registers controlled by the rising edge of the clock. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

is 2.6 ns (250 MHz device). CY7C1347G supports either the

interleaved burst sequence used by the Intel Pentium

processor or a linear burst sequence used by processors such

as the PowerPC

MODE pin. Accesses can be initiated by asserting either the

Address Strobe from Processor (ADSP) or the Address Strobe

from Controller (ADSC) at clock rise. Address advancement

through the burst sequence is controlled by the ADV input. A

2-bit on-chip wraparound burst counter captures the first

address in a burst sequence and automatically increments the

address for the rest of the burst access.

Byte write operations are qualified with the four Byte Write

Select (BW

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Selects (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to provide proper

data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

•

DDQ

200 MHz

San Jose

[A:D]

= 2.5V. All synchronous inputs pass through input

265

2.8

Guidelines.

) inputs. A Global Write Enable (GW) overrides

. The burst sequence is selected through the

CA 95134-1709

166 MHz

240

3.5

[1]

Revised May 22, 2007

, CE

CY7C1347G

133 MHz

•

225

4.0

, CE

408-943-2600

) and an

Unit

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