CY7C1355C-100BZC CYPRESS [Cypress Semiconductor], CY7C1355C-100BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1355C-100BZC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05688 Rev. *D
On the next clock rise the data presented to DQs (or a subset
for Byte Write operations, see Truth Table for details) inputs is
latched into the device and the write is complete. Additional
accesses (Read/Write/Deselect) can be initiated on this cycle.
The data written during the Write operation is controlled by
BW
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed write mechanism has been provided
to simplify the Write operations. Byte Write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple Byte Write opera-
tions.
Because the CY7C1379C is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs and DQP
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1379C has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.
ZZ Mode Electrical Characteristics
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
[A:D]
[A:D]
inputs must be driven in each cycle of the burst write,
signals. The CY7C1379C provides Byte Write
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to Sleep current
ZZ inactive to exit Sleep current
1
, CE
2
Description
, and CE
3
) and WE inputs are
X
.are
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
DD
DD
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
Linear Burst Address Table
(MODE = GND)
Interleaved Burst Sequence
Test Conditions
− 0.2V
− 0.2V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
11
00
01
10
11
ZZREC
Address
Address
Second
Second
A1, A0
A1, A0
1
01
10
00
01
00
10
, CE
11
11
after the ZZ input returns LOW.
2
, and CE
2t
Min.
Address
Address
CYC
0
A1, A0
A1, A0
3
Third
Third
, must remain inactive for
10
00
01
10
00
01
11
11
CY7C1379C
2t
2t
Max.
50
CYC
CYC
Page 6 of 15
Address
Address
Fourth
Fourth
A1, A0
A1, A0
11
00
01
10
11
10
01
00
Unit
mA
ns
ns
ns
ns